SiC SEMICONDUCTOR DEVICE

ABSTRACT

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.

TECHNICAL FIELD

The present invention relates to an SiC semiconductor device.

BACKGROUND ART

A method for processing an SiC semiconductor wafer called a stealthdicing method has come to be noted in recent years. With the stealthdicing method, after laser light is selectively irradiated onto the SiCsemiconductor wafer, the SiC semiconductor wafer is cut along theportion irradiated with the laser light. According to this method, theSiC semiconductor wafer, which has a comparatively high hardness, can becut without using a cutting member such as a dicing blade, etc., andtherefore a manufacturing time can be shortened.

Patent Literature 1 discloses a method for manufacturing an SiCsemiconductor device that uses the stealth dicing method. In themanufacturing method of Patent Literature 1, a plurality of columns ofmodified regions (modified layers) are formed over entire areas ofrespective side surfaces of an SiC semiconductor layer cut out from theSiC semiconductor wafer. The plurality of columns of modified regionsextend along tangential directions to a main surface of the SiCsemiconductor layer and are formed at intervals in a normal direction tothe main surface of the SiC semiconductor layer.

CITATION LIST Patent Literature

Patent Literature 1: Japanese Patent Application Publication No.2012-146878

SUMMARY OF INVENTION Technical Problem

The present inventors studied implementing of the stealth dicing methodto a structure having an insulating layer formed on a main surface of anSiC semiconductor wafer. In a case where a conventional method formanufacturing an SiC semiconductor device is applied to this structure,after modified layers are formed in an interior of the SiC semiconductorwafer, the SiC semiconductor wafer is cut together with the insulatinglayer with a modified layer as a cutting starting point.

The insulating layer, although having physical properties different froman SiC monocrystal, does not have a modified layer and is thus unlikelyto become a cutting starting point. Therefore, problems, such aslowering of adhesion force of the insulating layer, peeling of theinsulating layer, etc., occur due to impact during cutting of the SiCsemiconductor wafer. This problem remains in the SiC semiconductordevice cut out from the SiC semiconductor wafer.

One preferred embodiment of the present invention provides an SiCsemiconductor device where, in a structure having an insulating layerformed on an SiC semiconductor layer, peeling of the insulator layer canbe suppressed.

Solution to Problem

One preferred embodiment of the present invention provides an SiCsemiconductor device including an SiC semiconductor layer including anSiC monocrystal and having a first main surface as a device surface, asecond main surface at a side opposite to the first main surface, and aside surface connecting the first main surface and the second mainsurface, a main surface insulating layer including an insulatingmaterial, covering the first main surface of the SiC semiconductorlayer, and having an insulating side surface continuous to the sidesurface of the SiC semiconductor layer, and a boundary modified layerincluding a first region that is modified to be of a property differingfrom the SiC monocrystal and a second region that is modified to be of aproperty differing from the insulating material, and being formed acrossthe side surface of the SiC semiconductor layer and the insulating sidesurface of the main surface insulating layer.

According to this SiC semiconductor device, the boundary modified layerserved as a cutting starting point is formed across the SiCsemiconductor layer and the main surface insulating layer. Therefore,lowering of adhesion force of the main surface insulating layer, peelingof the main surface insulating layer, etc., due to impact during cuttingof the SiC semiconductor wafer can be suppressed in cutting out the SiCsemiconductor device from the SiC semiconductor wafer. The SiCsemiconductor device in which the peeling of the main surface insulatinglayer can be suppressed can thus be provided.

The aforementioned as well as yet other objects, features, and effectsof the present invention will be made clear by the following descriptionof the preferred embodiments, with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram of a unit cell of a 4H-SiC monocrystal to be appliedto preferred embodiments of the present invention.

FIG. 2 is a plan view of a silicon plane of the unit cell shown in FIG.1.

FIG. 3 is a perspective view as viewed from one angle of an SiCsemiconductor device according to a first preferred embodiment of thepresent invention and is a perspective view showing a firstconfiguration example of modified lines.

FIG. 4 is a perspective view as viewed from another angle of the SiCsemiconductor device shown in FIG. 3.

FIG. 5A is an enlarged view of a region VA shown in FIG. 3.

FIG. 5B is an enlarged view of a region VB shown in FIG. 3.

FIG. 6A is an enlarged view of a region VIA shown in FIG. 3.

FIG. 6B is an enlarged view of a region VIB shown in FIG. 3.

FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. 3.

FIG. 8 is a sectional view taken along line VIII-VIII shown in FIG. 7.

FIG. 9 is a perspective view showing an SiC semiconductor wafer used inmanufacturing the SiC semiconductor device shown in FIG. 3.

FIG. 10A is a sectional view of an example of a method for manufacturingthe SiC semiconductor device shown in FIG. 3.

FIG. 10B is a diagram of a step subsequent to that of FIG. 10A.

FIG. 100 is a diagram of a step subsequent to that of FIG. 10B.

FIG. 10D is a diagram of a step subsequent to that of FIG. 10C.

FIG. 10E is a diagram of a step subsequent to that of FIG. 10D.

FIG. 10F is a diagram of a step subsequent to that of FIG. 10E.

FIG. 10G is a diagram of a step subsequent to that of FIG. 10F.

FIG. 10H is a diagram of a step subsequent to that of FIG. 10G.

FIG. 10I is a diagram of a step subsequent to that of FIG. 10H.

FIG. 10J is a diagram of a step subsequent to that of FIG. 10I.

FIG. 10K is a diagram of a step subsequent to that of FIG. 10J.

FIG. 10L is a diagram of a step subsequent to that of FIG. 10K.

FIG. 10M is a diagram of a step subsequent to that of FIG. 10L.

FIG. 11 is a perspective view, as seen through a sealing resin, of asemiconductor package incorporating the SiC semiconductor device shownin FIG. 3.

FIG. 12A is a perspective view showing the SiC semiconductor deviceshown in FIG. 3 and is a perspective view showing a second configurationexample of the modified lines.

FIG. 12B is a perspective view showing the SiC semiconductor deviceshown in FIG. 3 and is a perspective view showing a third configurationexample of the modified lines.

FIG. 12C is a perspective view showing the SiC semiconductor deviceshown in FIG. 3 and is a perspective view showing a fourth configurationexample of the modified lines.

FIG. 12D is a perspective view showing the SiC semiconductor deviceshown in FIG. 3 and is a perspective view showing a fifth configurationexample of the modified lines.

FIG. 12E is a perspective view showing the SiC semiconductor deviceshown in FIG. 3 and is a perspective view showing a sixth configurationexample of the modified lines.

FIG. 12F is a perspective view showing the SiC semiconductor deviceshown in FIG. 3 and is a perspective view showing a seventhconfiguration example of the modified lines.

FIG. 13 is a perspective view showing an SiC semiconductor deviceaccording to a second preferred embodiment of the present invention andis a perspective view showing a structure applied with the modifiedlines according to the first configuration example.

FIG. 14 is an enlarged view of a region XIV shown in FIG. 13.

FIG. 15 is an enlarged view of a region XV shown in FIG. 13.

FIG. 16 is a perspective view as viewed from one angle of an SiCsemiconductor device according to a third preferred embodiment of thepresent invention and is a perspective view showing a structure appliedwith the modified lines according to the first configuration example.

FIG. 17 is a perspective view as viewed from another angle of the SiCsemiconductor device shown in FIG. 16.

FIG. 18 is a plan view of the SiC semiconductor device shown in FIG. 16.

FIG. 19 is a plan view with a resin layer removed from FIG. 18.

FIG. 20 is an enlarged view of a region XX shown in FIG. 19 and is adiagram for describing the structure of a first main surface of an SiCsemiconductor layer.

FIG. 21 is a sectional view taken along line XXI-XXI shown in FIG. 20.

FIG. 22 is a sectional view taken along line XXII-XXII shown in FIG. 20.

FIG. 23 is an enlarged view of a region XXIII shown in FIG. 21.

FIG. 24 is a sectional view taken along line XXIV-XXIV shown in FIG. 19.

FIG. 25 is an enlarged view of a region XXV shown in FIG. 24.

FIG. 26 is a graph for describing sheet resistance.

FIG. 27 is an enlarged view of a region corresponding to FIG. 20 and isan enlarged view of an SiC semiconductor device according to a fourthpreferred embodiment of the present invention.

FIG. 28 is a sectional view taken along line XXVIII-XXVIII shown in FIG.27.

FIG. 29 is an enlarged view of a region corresponding to FIG. 23 and isan enlarged view of an SiC semiconductor device according to a fifthpreferred embodiment of the present invention.

FIG. 30 is an enlarged view of a region corresponding to FIG. 20 and isan enlarged view of an SiC semiconductor device according to a sixthpreferred embodiment of the present invention.

FIG. 31 is a perspective view showing an SiC semiconductor deviceaccording to a seventh preferred embodiment of the present invention andis a perspective view showing a structure applied with the modifiedlines according to the first configuration example.

DESCRIPTION OF EMBODIMENTS

An SiC (silicon carbide) monocrystal constituted of a hexagonal crystalis applied in the preferred embodiments of the present invention. TheSiC monocrystal constituted of the hexagonal crystal has a plurality ofpolytypes including a 2H (hexagonal)-SiC monocrystal, a 4H-SiCmonocrystal, and a 6H-SiC monocrystal in accordance with cycle of atomicarrangement. Although, in the preferred embodiments of the presentinvention, examples where a 4H-SiC monocrystal is applied shall bedescribed, this does not exclude other polytypes from the presentinvention.

The crystal structure of the 4H-SiC monocrystal shall now be described.FIG. 1 is a diagram of a unit cell of the 4H-SiC monocrystal to beapplied to preferred embodiments of the present invention (hereinafterreferred to simply as the “unit cell”). FIG. 2 is a plan view of asilicon plane of the unit cell shown in FIG. 1.

Referring to FIG. 1 and FIG. 2, the unit cell includes tetrahedralstructures in each of which four C atoms are bonded to a single Si atomin a tetrahedral arrangement (regular tetrahedral arrangement)relationship. The unit cell has an atomic arrangement in which thetetrahedral structures are stacked in a four-period. The unit cell has ahexagonal prism structure having a regular hexagonal silicon plane, aregular hexagonal carbon plane, and six side planes connecting thesilicon plane and the carbon plane.

The silicon plane is an end plane terminated by Si atoms. At the siliconplane, a single Si atom is positioned at each of six vertices of aregular hexagon and a single Si atom is positioned at a center of theregular hexagon. The carbon plane is an end plane terminated by C atoms.At the carbon plane, a single C atom is positioned at each of sixvertices of a regular hexagon and a single C atom is positioned at acenter of the regular hexagon.

The crystal planes of the unit cell are defined by four coordinate axes(a1, a2, a3, and c) including an a1-axis, an a2-axis, an a3-axis, and ac-axis. Of the four coordinate axes, a value of a3 takes on a value of−(a1+a2). The crystal planes of the 4H-SiC monocrystal shall bedescribed below based on the silicon plane as an example of an end planeof a hexagonal crystal.

In a plan view of viewing the silicon plane from the c-axis, thea1-axis, the a2-axis, and the a3-axis are respectively set alongdirections of arrangement of the nearest neighboring Si atoms(hereinafter referred to simply as the “nearest atom directions”) basedon the Si atom positioned at the center. The a1-axis, the a2-axis, andthe a3-axis are set to be shifted by 120° each in conformance to thearrangement of the Si atoms.

The c-axis is set in a normal direction to the silicon plane based onthe Si atom positioned at the center. The silicon plane is a (0001)plane. The carbon plane is a (000-1) plane. The side planes of thehexagonal prism include six crystal planes oriented along the nearestatom directions in the plan view of viewing the silicon plane from thec-axis. More specifically, the side planes of the hexagonal prisminclude the six crystal planes each including two nearest neighboring Siatoms in the plan view of viewing the silicon plane from the c-axis.

In the plan view of viewing the silicon plane from the c-axis, the sideplanes of the unit cell include a (1-100) plane, a (0-110) plane, a(−1010) plane, a (−1100) plane, a (01-10) plane, and a (10-10) plane inclockwise order from a tip of the a1-axis.

Diagonal planes of the unit cell not passing through the center includesix crystal planes oriented along intersecting directions intersectingthe nearest atom directions in the plan view of viewing the siliconplane from the c-axis. When viewed on a basis of the Si atom positionedat the center, the nearest atom direction intersecting directions areorthogonal directions to the nearest atom directions. More specifically,the diagonal planes of the unit cell not passing through the centerinclude the six crystal planes that each include two Si atoms that arenot nearest neighbors.

In the plan view of viewing the silicon plane from the c-axis, thediagonal planes of the unit cell not passing through the center includea (11-20) plane, a (1-210) plane, a (−2110) plane, a (−1-120) plane, a(−12-10) plane, and a (2-1-10) plane.

The crystal directions of the unit cell are defined by directions normalto the crystal planes. A normal direction to the (1-100) plane is a[1-100] direction. A normal direction to the (0-110) plane is a [0-110]direction. A normal direction to the (−1010) plane is a [−1010]direction. A normal direction to the (−1100) plane is a [−1100]direction. A normal direction to the (01-10) plane is a [01-10]direction. A normal direction to the (10-10) plane is a [10-10]direction.

A normal direction to the (11-20) plane is a [11-20] direction. A normaldirection to the (1-210) plane is a [1-210] direction. A normaldirection to the (−2110) plane is a [−2110] direction. A normaldirection to the (−1-120) plane is a [−1-120] direction. A normaldirection to the (−12-10) plane is a [−12-10] direction. A normaldirection to the (2-1-10) plane is a [2-1-10] direction.

The hexagonal prism is six-fold symmetrical and has equivalent crystalplanes and equivalent crystal directions every 60°. For example, the(1-100) plane, the (0-110) plane, the (−1010) plane, the (−1100) plane,the (01-10) plane, and the (10-10) plane form equivalent crystal planes.Also, the (11-20) plane, the (1-210) plane, the (−2110) plane, the(−1-120) plane, the (−12-10) plane, and the (2-1-10) plane formequivalent crystal planes.

Also, the [1-100] direction, the [0-110] direction, the [−1010]direction, the [−1100] direction, the [01-10] direction, and the [10-10]direction form equivalent crystal directions. Also, the [11-20]direction, the [1-210] direction, the [−2110] direction, the [−1-120]direction, the [−12-10] direction, and the [2-1-10] direction formequivalent crystal directions.

The c-axis is a [0001] direction ([000-1] direction). The a1-axis is the[2-1-10] direction ([−2110] direction). The a2-axis is the [−12-10]direction ([1-210] direction). The a3-axis is the [−1-120] direction([11-20] direction).

The [0001] direction and the [000-1] direction are referred to as thec-axis. The (0001) plane and the (000-1) plane are referred to asc-planes. The [11-20] direction and the [−1-120] direction are referredto as an a-axis. The (11-20) plane and the (−1-120) plane are referredto as a-planes. The [1-100] direction and the [−1100] direction arereferred to as an m-axis. The (1-100) plane and the (−1100) plane arereferred to as m-planes.

FIG. 3 is a perspective view as viewed from one angle of an SiCsemiconductor device 1 according to a first preferred embodiment of thepresent invention and is a perspective view showing a firstconfiguration example of modified lines 22A to 22D. FIG. 4 is aperspective view as viewed from another angle of the SiC semiconductordevice 1 shown in FIG. 3. FIG. 5A is an enlarged view of a region VAshown in FIG. 3. FIG. 5B is an enlarged view of a region VB shown inFIG. 3. FIG. 6A is an enlarged view of a region VIA shown in FIG. 3.FIG. 6B is an enlarged view of a region VIB shown in FIG. 3. FIG. 7 is aplan view of the SiC semiconductor device 1 shown in FIG. 3. FIG. 8 is asectional view taken along line VIII-VIII shown in FIG. 7.

Referring to FIG. 3 to FIG. 8, the SiC semiconductor device 1 includesan SiC semiconductor layer 2. The SiC semiconductor layer 2 includes a4H-SiC monocrystal as an example of an SiC monocrystal constituted of ahexagonal crystal. The SiC semiconductor layer 2 is formed in a chipshape of rectangular parallelepiped shape.

The SiC semiconductor layer 2 has a first main surface 3 at one side, asecond main surface 4 at another side, and side surfaces 5A, 5B, 5C, and5D connecting the first main surface 3 and the second main surface 4.The first main surface 3 and the second main surface 4 are formed inquadrilateral shapes (square shapes here) in a plan view as viewed in anormal direction Z thereof (hereinafter referred to simply as “planview”).

The first main surface 3 is a device surface in which a functionaldevice (semiconductor element) is formed. The second main surface 4 isconstituted of a ground surface having grinding marks. The side surfaces5A to 5D are each constituted of a smooth cleavage surface facing acrystal plane of the SiC monocrystal. The side surfaces 5A to 5D arefree from a grinding mark.

A thickness TL of the SiC semiconductor layer 2 may be not less than 40μm and not more than 200 μm. The thickness TL may be not less than 40 μmand not more than 60 μm, not less than 60 μm and not more than 80 μm,not less than 80 μm and not more than 100 μm, not less than 100 μm andnot more than 120 μm, not less than 120 μm and not more than 140 μm, notless than 140 μm and not more than 160 μm, not less than 160 μm and notmore than 180 μm, or not less than 180 μm and not more than 200 μm. Thethickness TL is preferably not less than 60 μm and not more than 150 μm.

In this embodiment, the first main surface 3 and the second main surface4 face the c-planes of the SiC monocrystal. The first main surface 3faces the (0001) plane (silicon plane). The second main surface 4 facesthe (000-1) plane (carbon plane) of the SiC monocrystal.

The first main surface 3 and the second main surface 4 have an off angleθ inclined at an angle of not more than 10° in the [11-20] directionwith respect to the c-planes of the SiC monocrystal. The normaldirection Z is inclined by just the off angle θ with respect to thec-axis ([0001] direction) of the SiC monocrystal.

The off angle θ may be not less than 0° and not more than 5.0°. The offangle θ may be set in an angular range of not less than 0° and not morethan 1.0°, not less than 1.0° and not more than 1.5°, not less than 1.5°and not more than 2.0°, not less than 2.0° and not more than 2.5°, notless than 2.5° and not more than 3.0°, not less than 3.0° and not morethan 3.5°, not less than 3.5° and not more than 4.0°, not less than 4.0°and not more than 4.5°, or not less than 4.5° and not more than 5.0°.The off angle θ preferably exceeds 0°. The off angle θ may be less than4.0°.

The off angle θ may be set in an angular range of not less than 3.0° andnot more than 4.5°. In this case, the off angle θ is preferably set inan angular range of not less than 3.0° and not more than 3.5°, or notless than 3.5° and not more than 4.0°. The off angle θ may be set in anangular range of not less than 1.5° and not more than 3.0°. In thiscase, the off angle θ is preferably set in an angular range of not lessthan 1.5° and not more than 2.0°, or not less than 2.0° and not morethan 2.5°.

Lengths of the side surfaces 5A to 5D may each be not less than 0.5 mmand not more than 10 mm. Surface areas of the side surfaces 5A to 5D areequal to each other in this embodiment. If the first main surface 3 andthe second main surface 4 are formed in rectangular shapes in plan view,the surface areas of the side surfaces 5A and 5C may be less than thesurface areas of the side surfaces 5B and 5D or may exceed the surfaceareas of the side surfaces 5B and 5D.

In this embodiment, the side surface 5A and the side surface 5C extendin a first direction X and oppose each other in a second direction Yintersecting the first direction X. In this embodiment, the side surface5B and the side surface 5D extend in the second direction Y and opposeeach other in the first direction X. More specifically, the seconddirection Y is orthogonal to the first direction X.

In this embodiment, the first direction X is set to the m-axis direction([1-100] direction) of the SiC monocrystal. The second direction Y isset to the a-axis direction ([11-20] direction) of the SiC monocrystal.

The side surface 5A and the side surface 5C are formed by the a-planesof the SiC monocrystal and oppose each other in the a-axis direction.The side surface 5A is formed by the (−1-120) plane of the SiCmonocrystal. The side surface 5C is formed by the (11-20) plane of theSiC monocrystal. The side surface 5A and the side surface 5C may forminclined surfaces that, when a normal to the first main surface 3 istaken as a basis, are inclined toward the c-axis direction ([0001]direction) of the SiC monocrystal with respect to the normal.

In this case, the side surface 5A and the side surface 5C may beinclined at an angle in accordance with the off angle θ with respect tothe normal to the first main surface 3 when the normal to the first mainsurface 3 is 0°. The angle in accordance with the off angle θ may beequal to the off angle θ or may be an angle that exceeds 0° and is lessthan the off angle θ.

The side surface 5B and the side surface 5D are formed by the m-planesof the SiC monocrystal and oppose each other in the m-axis direction.The side surface 5B is formed by the (−1100) plane of the SiCmonocrystal. The side surface 5D is formed by the (1-100) plane of theSiC monocrystal. The side surface 5B and the side surface 5D extend inplane shapes along the normal to the first main surface 3. Morespecifically, the side surface 5B and the side surface 5D are formedsubstantially perpendicular to the first main surface 3 and the secondmain surface 4.

In this embodiment, the SiC semiconductor layer 2 has a laminatedstructure that includes an n⁺ type SiC semiconductor substrate 6 and ann type SiC epitaxial layer 7. The second main surface 4 of the SiCsemiconductor layer 2 is formed by the SiC semiconductor substrate 6.The first main surface 3 of the SiC semiconductor layer 2 is formed bythe SiC epitaxial layer 7. The side surfaces 5A to 5D of the SiCsemiconductor layer 2 are formed by the SiC semiconductor substrate 6and the SiC epitaxial layer 7.

An n type impurity concentration of the SiC epitaxial layer 7 is notmore than an n type impurity concentration of the SiC semiconductorsubstrate 6. More specifically, the n type impurity concentration of theSiC epitaxial layer 7 is less than the n type impurity concentration ofthe SiC semiconductor substrate 6. The n type impurity concentration ofthe SiC semiconductor substrate 6 may be not less than 1.0×10¹⁸ cm⁻³ andnot more than 1.0×10²¹ cm⁻³. The n type impurity concentration of theSiC epitaxial layer 7 may be not less than 1.0×10¹⁵ cm⁻³ and not morethan 1.0×10¹⁸ cm⁻³.

A thickness TS of the SiC semiconductor substrate 6 may be not less than40 μm and not more than 150 μm. The thickness TS may be not less than 40μm and not more than 50 μm, not less than 50 μm and not more than 60 μm,not less than 60 μm and not more than 70 μm, not less than 70 μm and notmore than 80 μm, not less than 80 μm and not more than 90 μm, not lessthan 90 μm and not more than 100 μm, not less than 100 μm and not morethan 110 μm, not less than 110 μm and not more than 120 μm, not lessthan 120 μm and not more than 130 μm, not less than 130 μm and not morethan 140 μm, or not less than 140 μm and not more than 150 μm. Thethickness TS is preferably not less than 40 μm and not more than 130 μm.By thinning the SiC semiconductor substrate 6, a current path isshortened and reduction of resistance value can thus be achieved.

A thickness TE of the SiC epitaxial layer 7 may be not less than 1 μmand not more than 50 μm. The thickness TE may be not less than 1 μm andnot more than 5 μm, not less than 5 μm and not more than 10 μm, not lessthan 10 μm and not more than 15 μm, not less than 15 μm and not morethan 20 μm, not less than 20 μm and not more than 25 μm, not less than25 μm and not more than 30 μm, not less than 30 μm and not more than 35μm, not less than 35 μm and not more than 40 μm, not less than 40 μm andnot more than 45 μm, or not less than 45 μm and not more than 50 μm. Thethickness TE is preferably not less than 5 μm and not more than 15 μm.

The SiC semiconductor layer 2 includes an active region 8 and an outerregion 9. The active region 8 is a region in which a Schottky barrierdiode D is formed as an example of a functional device. In plan view,the active region 8 is formed in a central portion of the SiCsemiconductor layer 2 at intervals toward an inner region from the sidesurfaces 5A to 5D of the SiC semiconductor layer 2. In plan view, theactive region 8 is formed in a quadrilateral shape having four sidesparallel to the four side surfaces 5A to 5D.

The outer region 9 is a region at an outer side of the active region 8.The outer region 9 is formed in a region between the side surfaces 5A to5D and peripheral edges of the active region 8. The outer region 9 isformed in an endless shape (a quadrilateral annular shape in thisembodiment) surrounding the active region 8 in plan view.

The SiC semiconductor device 1 includes a main surface insulating layer10 formed on the first main surface 3. The main surface insulating layer10 selectively covers the active region 8 and the outer region 9. Themain surface insulating layer 10 may have a single layer structureconstituted of a silicon oxide (SiO₂) layer or a silicon nitride (SiN)layer. The main surface insulating layer 10 may have a laminatedstructure that includes a silicon oxide layer and a silicon nitridelayer. The silicon oxide layer may be formed on the silicon nitridelayer. The silicon nitride layer may be formed on the silicon oxidelayer. In this embodiment, the main surface insulating layer 10 has asingle layer structure constituted of a silicon oxide layer.

The main surface insulating layer 10 has insulating side surfaces 11A,11B, 11C, and 11D exposed from the side surfaces 5A to 5D of the SiCsemiconductor layer 2. The insulating side surfaces 11A to 11D arecontinuous to the side surfaces 5A to 5D. The insulating side surfaces11A to 11D are formed flush with the side surfaces 5A to 5D. Theinsulating side surfaces 11A to 11D are constituted of cleavagesurfaces.

A thickness of the main surface insulating layer 10 may be not less than1 μm and not more than 50 μm. The thickness of the main surfaceinsulating layer 10 may be not less than 1 μm and not more than 10 μm,not less than 10 μm and not more than 20 μm, not less than 20 μm and notmore than 30 μm, not less than 30 μm and not more than 40 μm, or notless than 40 μm and not more than 50 μm.

The SiC semiconductor device 1 includes a first main surface electrodelayer 12 formed on the main surface insulating layer 10. In plan view,the first main surface electrode layer 12 is formed in the centralportion of the SiC semiconductor layer 2 at intervals toward the innerregion from the side surfaces 5A to 5D.

The SiC semiconductor device 1 includes a passivation layer 13(insulating layer) formed on the main surface insulating layer 10. Thepassivation layer 13 may have a single layer structure constituted of asilicon oxide layer or a silicon nitride layer. The passivation layer 13may have a laminated structure that includes a silicon oxide layer and asilicon nitride layer. The silicon oxide layer may be formed on thesilicon nitride layer. The silicon nitride layer may be formed on thesilicon oxide layer. In this embodiment, the passivation layer 13 has asingle layer structure constituted of a silicon nitride layer.

The passivation layer 13 includes four side surfaces 14A, 14B, 14C, and14D. In plan view, the side surfaces 14A to 14D of the passivation layer13 are formed at intervals toward the inner region from the sidesurfaces 5A to 5D of the SiC semiconductor layer 2. In plan view, thepassivation layer 13 exposes a peripheral edge portion of the first mainsurface 3. The passivation layer 13 exposes the main surface insulatinglayer 10.

The passivation layer 13 includes a sub pad opening 15 that exposes aportion of the first main surface electrode layer 12 as a pad region.The sub pad opening 15 is formed in a quadrilateral shape having foursides parallel to the side surfaces 5A to 5D in plan view.

A thickness of the passivation layer 13 may be not less than 1 μm andnot more than 50 μm. The thickness of the passivation layer 13 may benot less than 1 μm and not more than 10 μm, not less than 10 μm and notmore than 20 μm, not less than 20 μm and not more than 30 μm, not lessthan 30 μm and not more than 40 μm, or not less than 40 μm and not morethan 50 μm.

The SiC semiconductor device 1 includes a resin layer 16 (insulatinglayer) formed on the passivation layer 13. The resin layer 16, with thepassivation layer 13, forms a single insulating laminated structure(insulating layer). In FIG. 7, the resin layer 16 is shown withhatching.

The resin layer 16 may include a negative type or positive typephotosensitive resin. In this embodiment, the resin layer 16 includes apolybenzoxazole as an example of a positive type photosensitive resin.The resin layer 16 may include a polyimide as an example of a negativetype photosensitive resin.

The resin layer 16 includes four resin side surfaces 17A, 17B, 17C, and17D. In plan view, the resin side surfaces 17A to 17D of the resin layer16 are formed at intervals toward the inner region from the sidesurfaces 5A to 5D of the SiC semiconductor layer 2. In plan view, theresin layer 16 exposes the peripheral edge portion of the first mainsurface 3. The resin layer 16, together with the passivation layer 13,exposes the main surface insulating layer 10. In this embodiment, theresin side surfaces 17A to 17D of the resin layer 16 are formed flushwith the side surfaces 14A to 14D of the passivation layer 13.

The resin side surfaces 17A to 17D of the resin layer 16, with the sidesurfaces 5A to 5D of the SiC semiconductor layer 2, demarcate a dicingstreet. In this embodiment, the side surfaces 14A to 14D of thepassivation layer 13 also demarcate the dicing street. According to thedicing street, it is made unnecessary to physically cut the resin layer16 and the passivation layer 13 when cutting out the SiC semiconductordevice 1 from a single SiC semiconductor wafer. The SiC semiconductordevice 1 can thereby be cut out smoothly from the single SiCsemiconductor wafer. Also, insulation distances from the side surfaces5A to 5D can be increased.

A width of the dicing street may be not less than 1 μm and not more than25 μm. The width of the dicing street may be not less than 1 μm and notmore than 5 μm, not less than 5 μm and not more than 10 μm, not lessthan 10 μm and not more than 15 μm, not less than 15 μm and not morethan 20 μm, or not less than 20 μm and not more than 25 μm.

The resin layer 16 includes a pad opening 18 that exposes a portion ofthe first main surface electrode layer 12 as a pad region. The padopening 18 is formed in a quadrilateral shape having four sides parallelto the side surfaces 5A to 5D in plan view.

The pad opening 18 is in communication with the sub pad opening 15.Inner walls of the pad opening 18 are formed flush with inner walls ofthe sub pad opening 15. The inner walls of the pad opening 18 may bepositioned toward the side surface 5A to 5D sides with respect to theinner walls of the sub pad opening 15. The inner walls of the padopening 18 may be positioned toward the inner region of the SiCsemiconductor layer 2 with respect to the inner walls of the sub padopening 15. The resin layer 16 may cover the inner walls of the sub padopening 15.

A thickness of the resin layer 16 may be not less than 1 μm and not morethan 50 μm. The thickness of the resin layer 16 may be not less than 1μm and not more than 10 μm, not less than 10 μm and not more than 20 μm,not less than 20 μm and not more than 30 μm, not less than 30 μm and notmore than 40 μm, or not less than 40 μm and not more than 50 μm.

The SiC semiconductor device 1 includes a second main surface electrodelayer 19 formed on the second main surface 4 of the SiC semiconductorlayer 2. The second main surface electrode layer 19 forms an ohmiccontact with the second main surface 4 (SiC semiconductor substrate 6).

The SiC semiconductor device 1 includes a plurality of modified lines22A to 22D (modified layers) formed at the side surfaces 5A to 5D. Themodified lines 22A to 22D include one layer or a plurality (two layersor more; one layer in this embodiment) of the modified line 22A, onelayer or a plurality (two layers or more; one layer in this embodiment)of the modified line 22B, one layer or a plurality (two layers or more;one layer in this embodiment) of the modified line 22C, and one layer ora plurality (two layers or more; one layer in this embodiment) of themodified line 22D.

The modified lines 22A to 22D are formed in a relationship of one-to-onecorrespondence at the side surfaces 5A to 5D. The modified line 22A isformed at the side surface 5A. The modified line 22B is formed at theside surface 5B. The modified line 22C is formed at the side surface 5C.The modified line 22D is formed at the side surface 5D.

The modified lines 22A to 22D include regions of layer form in whichportions of the SiC monocrystal forming the side surfaces 5A to 5D aremodified to be of a property differing from the SiC monocrystal. Themodified lines 22A to 22D include the regions that are modified to be ofthe property differing in density, refractive index, mechanical strength(crystal strength), or other physical characteristic from the SiCmonocrystal. The modified lines 22A to 22D may include at least onelayer among a melted-and-rehardened layer, a defect layer, a dielectricbreakdown layer, and a refractive index change layer.

The melted-and-rehardened layer is a layer in which a portion of the SiCsemiconductor layer 2 is melted and thereafter hardened again. Thedefect layer is a layer that includes a hole, fissure, etc., formed inthe SiC semiconductor layer 2. The dielectric breakdown layer is a layerin which a portion of the SiC semiconductor layer 2 has undergonedielectric breakdown. The refractive index change layer is a layer inwhich a portion of the SiC semiconductor layer 2 is changed to arefractive index differing from the SiC monocrystal.

The modified lines 22A to 22D extend in band shapes along tangentialdirections to the first main surface 3. The tangential directions to thefirst main surface 3 are directions orthogonal to the normal directionZ. The tangential directions include the first direction X (the m-axisdirection of the SiC monocrystal) and the second direction Y (the a-axisdirection of the SiC monocrystal).

More specifically, the modified line 22A is formed in a band shapeextending rectilinearly along the m-axis direction at the side surface5A. The modified line 22B is formed in a band shape extendingrectilinearly along the a-axis direction at the side surface 5B. Themodified line 22C is formed in a band shape extending rectilinearlyalong the m-axis direction at the side surface 5C. The modified line 22Dis formed in a band shape extending rectilinearly along the a-axisdirection at the side surface 5D.

The modified lines 22A to 22D are formed at intervals toward the secondmain surface 4 side from the first main surface 3. The modified lines22A to 22D expose surface layer portions of the first main surface 3from the side surfaces 5A to 5D. The modified lines 22A to 22D areformed at intervals toward the first main surface 3 side from the secondmain surface 4. The modified lines 22A to 22D expose surface layerportions of the second main surface 4 from the side surfaces 5A to 5D.

The modified lines 22A to 22D are formed in thickness directionintermediate portions of the SiC semiconductor substrate 6 in the normaldirection Z. The modified lines 22A to 22D are formed at intervalstoward the second main surface 4 side from a boundary between the SiCsemiconductor substrate 6 and the SiC epitaxial layer 7. The modifiedlines 22A to 22D thereby expose the SiC epitaxial layer 7 at the surfacelayer portions of the first main surface 3.

Stripe patterns extending in the tangential directions of the first mainsurface 3 are formed in the respective side surfaces 5A to 5D by themodified lines 22A to 22D, the surface layer portions of the first mainsurface 3, and the surface layer portions of the second main surface 4.

The modified line 22A and the modified line 22B are continuous to eachother at a corner portion connecting the side surface 5A and the sidesurface 5B. The modified line 22B and the modified line 22C arecontinuous to each other at a corner portion connecting the side surface5B and the side surface 5C. The modified line 22C and the modified line22D are continuous to each other at a corner portion connecting the sidesurface 5C and the side surface 5D. The modified line 22D and themodified line 22A are continuous to each other at a corner portionconnecting the side surface 5D and the side surface 5A.

The modified lines 22A to 22D are thereby formed integrally such as tosurround the SiC semiconductor layer 2. The modified lines 22A to 22Dform a single endless (annular) modified line surrounding the SiCsemiconductor layer 2 at the side surfaces 5A to 5D.

In the normal direction Z, thicknesses TR of the modified lines 22A to22D are preferably not more than the thickness TL of the SiCsemiconductor layer 2 (TRTL). The thicknesses TR of the modified lines22A to 22D are more preferably less than the thickness TS of the SiCsemiconductor substrate 6 (TR<TS).

The thicknesses TR of the modified lines 22A to 22D may be not less thanthe thickness TE of the SiC epitaxial layer (TR≥TE). The thickness TR ofthe modified line 22A, the thickness TR of the modified line 22B, thethickness TR of the modified line 22C, and the thickness TR of themodified line 22D may be mutually equal or may be mutually different.

Ratios TR/TL of the thicknesses TR of the modified lines 22A to 22D withrespect to the thickness TL of the SiC semiconductor layer 2 arepreferably not less than 0.1 and less than 1.0. The ratios TR/TL may benot less than 0.1 and not more than 0.2, not less than 0.2 and not morethan 0.4, not less than 0.4 and not more than 0.6, not less than 0.6 andnot more than 0.8, or not less than 0.8 and less than 1.0.

The ratios TR/TL may be not less than 0.1 and not more than 0.2, notless than 0.2 and not more than 0.3, not less than 0.3 and not more than0.4, not less than 0.4 and not more than 0.5, not less than 0.5 and notmore than 0.6, not less than 0.6 and not more than 0.7, not less than0.7 and not more than 0.8, not less than 0.8 and not more than 0.9, ornot less than 0.9 and less than 1.0. The ratios TR/TL are preferably notless than 0.2 and not more than 0.5.

More preferably, ratios TR/TS of the thicknesses TR of the modifiedlines 22A to 22D with respect to the thickness TS of the SiCsemiconductor substrate 6 are not less than 0.1 and less than 1.0. Theratios TR/TS may be not less than 0.1 and not more than 0.2, not lessthan 0.2 and not more than 0.4, not less than 0.4 and not more than 0.6,not less than 0.6 and not more than 0.8, or not less than 0.8 and lessthan 1.0.

The ratios TR/TS may be not less than 0.1 and not more than 0.2, notless than 0.2 and not more than 0.3, not less than 0.3 and not more than0.4, not less than 0.4 and not more than 0.5, not less than 0.5 and notmore than 0.6, not less than 0.6 and not more than 0.7, not less than0.7 and not more than 0.8, not less than 0.8 and not more than 0.9, ornot less than 0.9 and less than 1.0. The ratios TR/TS are preferably notless than 0.2 and not more than 0.5.

Referring to FIG. 5A, the modified line 22A includes a plurality ofa-plane modified portions 28 (modified portions). In other words, themodified line 22A is formed of an aggregate of the plurality of a-planemodified portions 28. The plurality of a-plane modified portions 28 areportions at which the SiC monocrystal exposed from the side surface 5Ais modified to be of the property differing from the SiC monocrystal. Atthe side surface 5A, a region in a periphery of each a-plane modifiedportion 28 may be modified to be of a property differing from the SiCmonocrystal.

The plurality of a-plane modified portions 28 each include one endportion 28 a positioned at the first main surface 3 side, another endportion 28 b positioned at the second main surface 4 side, and aconnecting portion 28 c connecting the one end portion 28 a and theother end portion 28 b.

The plurality of a-plane modified portions 28 are each formed in alinear shape extending in the normal direction Z. The plurality ofa-plane modified portions 28 are thereby formed in a stripe shape as awhole. The plurality of a-plane modified portions 28 may include aplurality of a-plane modified portions 28 formed in a convergent shapein which the m-axis direction width narrows from the one end portion 28a side to the other end portion 28 b side.

The plurality of a-plane modified portions 28 are formed at intervals inthe m-axis direction such as to oppose each other in the m-axisdirection. The plurality of a-plane modified portions 28 may beoverlapped mutually in the m-axis direction. A band-shaped regionextending in the m-axis direction is formed by a line joining the oneend portions 28 a of the plurality of a-plane modified portions 28 and aline joining the other end portions 28 b of the plurality of a-planemodified portions 28. The modified line 22A is formed by thisband-shaped region.

The plurality of a-plane modified portions 28 may each form a notchedportion at which the side surface 5A is notched. The plurality ofa-plane modified portions 28 may each form a recess recessed toward thea-axis direction from the side surface 5A. The plurality of a-planemodified portions 28 may be formed in point shapes (dot shapes) inaccordance with length in the normal direction Z and the m-axisdirection width.

A pitch PR in the m-axis direction between central portions of aplurality of mutually adjacent a-plane modified portions 28 may exceed 0μm and be not more than 20 μm. The pitch PR may exceed 0 μm and be notmore than 5 μm, be not less than 5 μm and not more than 10 μm, be notless than 10 μm and not more than 15 μm, or be not less than 15 μm andnot more than 20 μm.

A width WR in the m-axis direction of each a-plane modified portion 28may exceed 0 μm and be not more than 20 μm. The width WR may exceed 0 μmand be not more than 5 μm, be not less than 5 μm and not more than 10μm, be not less than 10 μm and not more than 15 μm, or be not less than15 μm and not more than 20 μm.

The modified line 22C has the same structure as the modified line 22Awith the exception of the point of being formed at the side surface 5C.The description of the modified line 22A applies to the description ofthe modified line 22C upon replacement of “side surface 5A” by “sidesurface 5C.”

Referring to FIG. 6A, the modified line 22D includes a plurality ofm-plane modified portions 29 (modified portions). In other words, themodified line 22D is formed of an aggregate of the plurality of m-planemodified portions 29. The plurality of m-plane modified portions 29 areportions at which the SiC monocrystal exposed from the side surface 5Dis modified to be of the property differing from the SiC monocrystal. Atthe side surface 5D, a region in a periphery of each m-plane modifiedportion 29 may be modified to be of a property differing from the SiCmonocrystal.

The plurality of m-plane modified portions 29 each include one endportion 29 a positioned at the first main surface 3 side, another endportion 29 b positioned at the second main surface 4 side, and aconnecting portion 29 c connecting the one end portion 29 a and theother end portion 29 b.

The plurality of m-plane modified portions 29 are each formed in alinear shape extending in the normal direction Z. The plurality ofm-plane modified portions 29 are thereby formed in a stripe shape as awhole. The plurality of m-plane modified portions 29 may include aplurality of m-plane modified portions 29 formed in a convergent shapein which an a-axis direction width narrows from the one end portion 29 aside to the other end portion 29 b side.

The plurality of m-plane modified portions 29 are formed at intervals inthe a-axis direction such as to oppose each other in the a-axisdirection. The plurality of m-plane modified portions 29 may beoverlapped mutually in the a-axis direction. A band-shaped regionextending in the a-axis direction is formed by a line joining the oneend portions 29 a of the plurality of m-plane modified portions 29 and aline joining the other end portions 29 b of the plurality of m-planemodified portions 29. The modified line 22D is formed by thisband-shaped region.

The plurality of m-plane modified portions 29 may each form a notchedportion at which the side surface 5D is notched. The plurality ofm-plane modified portions 29 may each form a recess recessed toward them-axis direction from the side surface 5D. The plurality of m-planemodified portions 29 may be formed in point shapes (dot shapes) inaccordance with length in the normal direction Z and the a-axisdirection width.

A pitch PR in the a-axis direction between central portions of aplurality of mutually adjacent m-plane modified portions 29 may be notless than 0 μm and not more than 20 μm. The pitch PR may be not lessthan 0 μm and not more than 5 μm, not less than 5 μm and not more than10 μm, not less than 10 μm and not more than 15 μm, or not less than 15μm and not more than 20 μm.

A width WR in the a-axis direction of each m-plane modified portion 29may exceed 0 μm and be not more than 20 μm. The width WR may exceed 0 μmand be not more than 5 μm, be not less than 5 μm and not more than 10μm, be not less than 10 μm and not more than 15 μm, or be not less than15 μm and not more than 20 μm.

The modified line 22B has the same structure as the modified line 22Dwith the exception of the point of being formed at the side surface 5B.The description of the modified line 22D applies to the description ofthe modified line 22B upon replacement of “side surface 5D” by “sidesurface 5B.”

Referring to FIG. 3, FIG. 4, FIG. 5B, and FIG. 6B, the SiC semiconductordevice 1 includes a plurality of boundary modified lines 30A to 30D(boundary modified layers) formed at the side surfaces 5A to 5D of theSiC semiconductor layer 2 and the insulating side surfaces 11A to 11D ofthe main surface insulating layer 10.

The boundary modified lines 30A to 30D are formed across the sidesurfaces 5A to 5D and the insulating side surfaces 11A to 11D. Theboundary modified lines 30A to 30D are formed across the side surfaces5A to 5D and the insulating side surfaces 11A to 11D while avoiding thepassivation layer 13 and the resin layer 16. That is, the boundarymodified lines 30A to 30D are not formed in the passivation layer 13 andthe resin layer 16.

The boundary modified lines 30A to 30D include one layer or a plurality(two layers or more; one layer in this embodiment) of the boundarymodified line 30A, one layer or a plurality (two layers or more; onelayer in this embodiment) of the boundary modified line 30B, one layeror a plurality (two layers or more; one layer in this embodiment) of theboundary modified line 30C, and one layer or a plurality (two layers ormore; one layer in this embodiment) of the boundary modified line 30D.

The boundary modified lines 30A to 30D are formed in a relationship ofone-to-one correspondence in boundary regions between the side surfaces5A to 5D and the insulating side surfaces 11A to 11D. The boundarymodified line 30A is formed in the boundary region between the sidesurface 5A and the insulating side surface 11A. The boundary modifiedline 30B is formed in the boundary region between the side surface 5Band the insulating side surface 11B. The boundary modified line 30C isformed in the boundary region between the side surface 5C and theinsulating side surface 11C. The boundary modified line 30D is formed inthe boundary region between the side surface 5D and the insulating sidesurface 11D.

The boundary modified lines 30A to 30D are positioned at the first mainsurface 3 side with respect to the modified lines 22A to 22D. Theboundary modified lines 30A to 30D oppose the modified lines 22A to 22Dalong the normal direction Z.

In this embodiment, the boundary modified lines 30A to 30D are formed atintervals from the modified lines 22A to 22D. The boundary modifiedlines 30A to 30D may be overlapped with the modified lines 22A to 22D.The boundary modified lines 30A to 30D may be continuous to the modifiedlines 22A to 22D.

The boundary modified lines 30A to 30D may be formed integral to themodified lines 22A to 22D. In this case, the boundary modified lines 30Ato 30D serving in common as the modified lines 22A to 22D may be formed.More specifically, the boundary modified lines 30A to 30D may extendfrom the boundary regions between the side surfaces 5A to 5D and theinsulating side surfaces 11A to 11D to thickness direction intermediateportions of the SiC semiconductor layer 2 (SiC semiconductor substrate6).

The boundary modified lines 30A to 30D extend in band shapes along thetangential directions to the first main surface 3. The boundary modifiedlines 30A to 30D extend parallel to the modified lines 22A to 22D.

The boundary modified line 30A is formed in a band shape extendingrectilinearly along the m-axis direction at the side surface 5A and theinsulating side surface 11A. The boundary modified line 30B is formed ina band shape extending rectilinearly along the a-axis direction at theside surface 5B and the insulating side surface 11B.

The boundary modified line 30C is formed in a band shape extendingrectilinearly along the m-axis direction at the side surface 5C and theinsulating side surface 11C. The boundary modified line 30D is formed ina band shape extending rectilinearly along the a-axis direction at theside surface 5D and the insulating side surface 11D.

The boundary modified lines 30A to 30D include first regions 31 at theside surface 5A to 5D sides and second regions 32 at the insulating sidesurface 11A to 11D sides. The first regions 31 include regions of layerform in which portions of the SiC monocrystal forming the side surfaces5A to 5D are modified to be of a property differing from the SiCmonocrystal.

The second regions 32 include regions of layer form in which portions ofan insulating material forming the insulating side surfaces 11A to 11Dare modified to be of a property differing from the insulating material.The second regions 32 are continuous to the first regions 31. Also, thesecond regions 32 are integral to the first regions 31. The secondregions 32 may be adhered, fixed, welded and/or fused to the firstregions 31.

The first regions 31 include the regions that are modified to be of theproperty differing in density, refractive index, mechanical strength(crystal strength), or other physical characteristic from the SiCmonocrystal. The first regions 31 may include at least one layer among amelted-and-rehardened layer, a defect layer, a dielectric breakdownlayer, and a refractive index change layer.

The melted-and-rehardened layer is a layer in which a portion of the SiCsemiconductor layer 2 is melted and thereafter hardened again. Thedefect layer is a layer that includes a hole, fissure, etc., formed inthe SiC semiconductor layer 2. The dielectric breakdown layer is a layerin which a portion of the SiC semiconductor layer 2 has undergonedielectric breakdown. The refractive index change layer is a layer inwhich a portion of the SiC semiconductor layer 2 is changed to arefractive index differing from the SiC monocrystal.

The second regions 32 include the regions that are modified to be of theproperty differing in density, refractive index, mechanical strength(crystal strength), or other physical characteristic from the insulatingmaterial of the main surface insulating layer 10. The second regions 32may include at least one layer among a melted-and-rehardened layer, adefect layer, a dielectric breakdown layer, and a refractive indexchange layer.

The melted-and-rehardened layer is a layer in which a portion of themain surface insulating layer 10 is melted and thereafter hardenedagain. The defect layer is a layer that includes a hole, fissure, etc.,formed in the main surface insulating layer 10. The dielectric breakdownlayer is a layer in which a portion of the main surface insulating layer10 has undergone dielectric breakdown. The refractive index change layeris a layer in which a portion of the main surface insulating layer 10 ischanged to a refractive index differing from the insulating material ofthe main surface insulating layer 10.

In this embodiment, the first regions 31 of the boundary modified lines30A to 30D are formed at intervals toward the first main surface 3 sidefrom the modified lines 22A to 22D. The first regions 31 are formed atintervals toward the first main surface 3 side from a boundary region ofthe SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

The first regions 31 thereby expose portions of the SiC epitaxial layer7 from the side surfaces 5A to 5D. The first regions 31 may cross theboundary region of the SiC semiconductor substrate 6 and the SiCepitaxial layer 7 and be formed in both the SiC semiconductor substrate6 and the SiC epitaxial layer 7. In this case, the first regions 31 maybe overlapped with the modified lines 22A to 22D.

The first region 31 of the boundary modified line 30A and the firstregion 31 of the boundary modified line 30B are continuous to each otherat the corner portion connecting the side surface 5A and the sidesurface 5B. The first region 31 of the boundary modified line 30B andthe first region 31 of the boundary modified line 30C are continuous toeach other at the corner portion connecting the side surface 5B and theside surface 5C.

The first region 31 of the boundary modified line 30C and the firstregion 31 of the boundary modified line 30D are continuous to each otherat the corner portion connecting the side surface 5C and the sidesurface 5D. The first region 31 of the boundary modified line 30D andthe first region 31 of the boundary modified line 30A are continuous toeach other at the corner portion connecting the side surface 5D and theside surface 5A.

The first regions 31 of the boundary modified lines 30A to 30D arethereby formed integrally such as to surround the SiC semiconductorlayer 2. That is, the first regions 31 of the boundary modified lines30A to 30D forma single endless (annular) boundary modified linesurrounding the SiC semiconductor layer 2 at the side surfaces 5A to 5D.

In this embodiment, the second regions 32 of the boundary modified lines30A to 30D are formed at intervals toward the SiC semiconductor layer 2side from a main surface of the main surface insulating layer 10. Thesecond regions 32 thereby expose surface layer portions of the mainsurface of the main surface insulating layer 10 from the insulating sidesurfaces 11A to 11D. The second regions 32 may be formed over entireareas of the insulating side surfaces 11A to 11D.

The second region 32 of the boundary modified line 30A and the secondregion 32 of the boundary modified line 30B are continuous to each otherat a corner portion connecting the insulating side surface 11A and theinsulating side surface 11B. The second region 32 of the boundarymodified line 30B and the second region 32 of the boundary modified line30C are continuous to each other at a corner portion connecting theinsulating side surface 11B and the insulating side surface 11C.

The second region 32 of the boundary modified line 30C and the secondregion 32 of the boundary modified line 30D are continuous to each otherat a corner portion connecting the insulating side surface 110 and theinsulating side surface 11D. The second region 32 of the boundarymodified line 30D and the second region 32 of the boundary modified line30A are continuous to each other at a corner portion connecting theinsulating side surface 11D and the insulating side surface 11A.

The second regions 32 of the boundary modified lines 30A to 30D arethereby formed integrally such as to surround the main surfaceinsulating layer 10. That is, the second regions 32 of the boundarymodified lines 30A to 30D form a single endless (annular) boundarymodified line surrounding the main surface insulating layer 10 at theinsulating side surfaces 11A to 11D.

In the normal direction Z, thicknesses TRB of the boundary modifiedlines 30A to 30D are preferably less than the thickness TS of the SiCsemiconductor substrate 6 (TRB<TS). The thicknesses TRB of the boundarymodified lines 30A to 30D may be not more than the thicknesses TR of themodified lines 22A to 22D (TRB≤TR). The thicknesses TRB of the boundarymodified lines 30A to 30D may be not more than the thickness TE of theSiC epitaxial layer 7 (TRB≤TE).

The thickness TRB of the boundary modified line 30A, the thickness TRBof the boundary modified line 30B, the thickness TRB of the boundarymodified line 30C, and the thickness TRB of the boundary modified line30D may be mutually equal or may be mutually different.

Ratios TRB/TL of the thicknesses TRB of the boundary modified lines 30Ato 30D with respect to the thickness TL of the SiC semiconductor layer 2may be not less than 0.01 and less than 1.0. The ratios TRB/TL may benot less than 0.01 and not more than 0.02, not less than 0.02 and notmore than 0.04, not less than 0.04 and not more than 0.06, not less than0.06 and not more than 0.08, or not less than 0.08 and not more than0.1. The ratios TRB/TL may be not less than 0.1 and not more than 0.2,not less than 0.2 and not more than 0.4, not less than 0.4 and not morethan 0.6, not less than 0.6 and not more than 0.8, or not less than 0.8and less than 1.0.

Referring to FIG. 5B, the boundary modified line 30A includes aplurality of a-plane boundary modified portions (boundary modifiedportions) crossing a boundary region between the SiC semiconductor layer2 and the main surface insulating layer 10. In other words, the boundarymodified line 30A is formed of an aggregate of the plurality of a-planeboundary modified portions 33.

The plurality of a-plane boundary modified portions 33 are portions atwhich the SiC monocrystal exposed from the side surface 5A is modifiedto be of the property differing from the SiC monocrystal and theinsulating material exposed from the insulating side surface 11A ismodified to be of the property differing from the insulating material.

At the side surface 5A, a region in a periphery of each a-plane boundarymodified portion 33 may be modified to be of a property differing fromthe SiC monocrystal. At the insulating side surface 11A, a region in aperiphery of each a-plane boundary modified portion 33 may be modifiedto be of a property differing from the insulating material of the mainsurface insulating layer 10.

The plurality of a-plane boundary modified portions 33 each include oneend portion 33 a positioned at the main surface insulating layer 10,another end portion 33 b positioned at the SiC semiconductor layer 2,and a connecting portion 33 c connecting the one end portion 33 a andthe other end portion 33 b. The connecting portion 33 c crosses theboundary region between the SiC semiconductor layer 2 and the mainsurface insulating layer 10 to connect the one end portion 33 a and theother end portion 33 b.

The plurality of a-plane boundary modified portions 33 are each formedin a linear shape extending in the normal direction Z. The plurality ofa-plane boundary modified portions 33 are thereby formed in a stripeshape as a whole. The plurality of a-plane boundary modified portions 33may include a plurality of a-plane boundary modified portions 33 formedin a convergent shape in which an m-axis direction width narrows fromthe one end portion 33 a side to the other end portion 33 b side.

The plurality of a-plane boundary modified portions 33 are formed atintervals in the m-axis direction such as to oppose each other in them-axis direction. The plurality of a-plane boundary modified portions 33may be overlapped mutually in the m-axis direction. A band-shaped regionextending in the m-axis direction is formed by a line joining the oneend portions 33 a of the plurality of a-plane boundary modified portions33 and a line joining the other end portions 33 b of the plurality ofa-plane boundary modified portions 33. The boundary modified line 30A isformed by this band-shaped region.

The plurality of a-plane boundary modified portions 33 may each form anotched portion at which the side surface 5A and the insulating sidesurface 11A are notched. The plurality of a-plane boundary modifiedportions 33 may each form a recess recessed toward the a-axis directionfrom the side surface 5A and the insulating side surface 11A. Theplurality of a-plane boundary modified portions 33 may be formed inpoint shapes (dot shapes) in accordance with length in the normaldirection Z and the m-axis direction width.

A pitch PRB in the m-axis direction between central portions of aplurality of mutually adjacent a-plane boundary modified portions 33 mayexceed 0 μm and be not more than 20 μm. The pitch PRB may exceed 0 μmand be not more than 5 μm, be not less than 5 μm and not more than 10μm, be not less than 10 μm and not more than 15 μm, or be not less than15 μm and not more than 20 μm.

A width WRB in the m-axis direction of each a-plane boundary modifiedportion 33 may exceed 0 μm and be not more than 20 μm. The width WRB mayexceed 0 μm and be not more than 5 μm, be not less than 5 μm and notmore than 10 μm, be not less than 10 μm and not more than 15 μm, or benot less than 15 μm and not more than 20 μm.

The boundary modified line 30C has the same structure as the boundarymodified line 30A with the exception of the point of being formed at theside surface 5C and the insulating side surface 11C. The description ofthe boundary modified line 30A applies to the description of theboundary modified line 30C upon replacement of “side surface 5A” and“insulating side surface 11A” by “side surface 5C” and “insulating sidesurface 11C,” respectively.

Referring to FIG. 6B, the boundary modified line 30D includes aplurality of m-plane boundary modified portions 34 (boundary modifiedportions) crossing the boundary region between the SiC semiconductorlayer 2 and the main surface insulating layer 10. In other words, theboundary modified line 30D is formed of an aggregate of the plurality ofm-plane boundary modified portions 34.

The plurality of m-plane boundary modified portions 34 are portions atwhich the SiC monocrystal exposed from the side surface 5D is modifiedto be of the property differing from the SiC monocrystal and theinsulating material exposed from the insulating side surface 11D ismodified to be of the property differing from the insulating material.

At the side surface 5D, a region in a periphery of each m-plane boundarymodified portion 34 may be modified to be of a property differing fromthe SiC monocrystal. At the insulating side surface 11D, a region in aperiphery of each m-plane boundary modified portion 34 may be modifiedto be of a property differing from the insulating material of the mainsurface insulating layer 10.

The plurality of m-plane boundary modified portions 34 each include oneend portion 34 a positioned at the SiC semiconductor layer 2, anotherend portion 34 b positioned at the main surface insulating layer 10, anda connecting portion 34 c connecting the one end portion 34 a and theother end portion 34 b. The connecting portion 34 c crosses the boundaryregion between the SiC semiconductor layer 2 and the main surfaceinsulating layer 10 to connect the one end portion 34 a and the otherend portion 34 b.

The plurality of m-plane boundary modified portions 34 are each formedin a linear shape extending in the normal direction Z. The plurality ofm-plane boundary modified portions 34 are thereby formed in a stripeshape as a whole. The plurality of m-plane boundary modified portions 34may include a plurality of m-plane boundary modified portions 34 formedin a convergent shape in which an m-axis direction width narrows fromthe one end portion 34 a side to the other end portion 34 b side.

The plurality of m-plane boundary modified portions 34 are formed atintervals in the a-axis direction such as to oppose each other in thea-axis direction. The plurality of m-plane boundary modified portions 34may be overlapped mutually in the a-axis direction. A band-shaped regionextending in the a-axis direction is formed by a line joining the oneend portions 34 a of the plurality of m-plane boundary modified portions34 and a line joining the other end portions 34 b of the plurality ofm-plane boundary modified portions 34. The boundary modified line 30D isformed by this band-shaped region.

The plurality of m-plane boundary modified portions 34 may each form anotched portion at which the side surface 5D and the insulating sidesurface 11D are notched. The plurality of m-plane boundary modifiedportions 34 may each form a recess recessed toward the m-axis directionfrom the side surface 5D and the insulating side surface 11D. Theplurality of m-plane boundary modified portions 34 may be formed inpoint shapes (dot shapes) in accordance with length in the normaldirection Z and the a-axis direction width.

A pitch PRB in the a-axis direction between central portions of aplurality of mutually adjacent m-plane boundary modified portions 34 mayexceed 0 μm and be not more than 20 μm. The pitch PRB may exceed 0 μmand be not more than 5 μm, be not less than 5 μm and not more than 10μm, be not less than 10 μm and not more than 15 μm, or be not less than15 μm and not more than 20 μm.

A width WRB in the a-axis direction of each m-plane boundary modifiedportion 34 may exceed 0 μm and be not more than 20 μm. The width WRB mayexceed 0 μm and be not more than 5 μm, be not less than 5 μm and notmore than 10 μm, be not less than 10 μm and not more than 15 μm, or benot less than 15 μm and not more than 20 μm.

The boundary modified line 30B has the same structure as the boundarymodified line 30D with the exception of the point of being formed at theside surface 5B and the insulating side surface 11B. The description ofthe boundary modified line 30D applies to the description of theboundary modified line 30B upon replacement of “side surface 5D” and“insulating side surface 11D” by “side surface 5B” and “insulating sidesurface 11B.”

The boundary modified lines 30A to 30D are preferably fixed to the sidesurfaces 5A to 5D and the insulating side surfaces 11A to 11D. In otherwords, the insulating side surfaces 11A to 11D are preferably fixed tothe side surfaces 5A to 5D by the boundary modified lines 30A to 30D. Inthis case, peeling of the main surface insulating layer 10 can besuppressed appropriately. That is, the SiC semiconductor device 1preferably includes a fixing layer that is formed by the boundarymodified lines 30A to 30D and fixes the side surfaces 5A to 5D and theinsulating side surfaces 11A to 11D.

The fixing layer may include a weld layer welded to the side surfaces 5Ato 5D and the insulating side surfaces 11A to 11D. The fixing layer mayinclude an insulating weld portion in which the insulating materialmelted from the main surface insulating layer 10 is welded to the sidesurfaces 5A to 5D. The insulating weld portion includes amelted-and-rehardened layer of the insulating material. The insulatingweld portion may be an insulating fused portion.

The fixing layer may include an SiC weld portion in which the SiCmonocrystal melted from the SiC semiconductor layer 2 is welded to theinsulating side surfaces 11A to 11D. The SiC weld portion includes amelted-and-rehardened layer of the SiC monocrystal. The SiC weld portionmay be an SiC fused portion. The fixing layer may include both theinsulating weld portion and the SiC weld portion.

The fixing layer may be formed by the first regions 31 and the secondregions 32 of the boundary modified lines 30A to 30D. The fixing layermay be formed by the a-plane boundary modified portions 33 and them-plane boundary modified portions 34. The fixing layer may include aportion or all of the boundary modified lines 30A to 30D.

Referring to FIG. 8, the SiC semiconductor device 1 includes an n typediode region 35 formed in a surface layer portion of the first mainsurface 3 in the active region 8. In this embodiment, the diode region35 is formed in a central portion of the first main surface 3. The dioderegion 35 may be formed in a quadrilateral shape having four sidesparallel to the side surfaces 5A to 5D in plan view.

In this embodiment, the diode region 35 is formed using a portion of theSiC epitaxial layer 7. An n type impurity concentration of the dioderegion 35 is equal to the n type impurity concentration of the SiCepitaxial layer 7. The n type impurity concentration of the diode region35 may be not less than the n type impurity concentration of the SiCepitaxial layer 7. That is, the diode region 35 may be formed byintroduction of an n type impurity into a surface layer portion of theSiC epitaxial layer 7.

The SiC semiconductor device 1 includes a p⁺ type guard region 36 formedin a surface layer portion of the first main surface 3 in the outerregion 9. The guard region 36 is formed in a band shape extending alongthe diode region 35 in plan view. More specifically, the guard region 36is formed in an endless shape surrounding the diode region 35 in planview. The guard region 36 is formed in a quadrilateral annular shape(more specifically, a quadrilateral annular shape with chamfered cornerportions or a circular annular shape).

The guard region 36 is thereby formed as a guard ring region. In thisembodiment, the diode region 35 is defined by the guard region 36. Also,the active region 8 is defined by the guard region 36.

A p type impurity of the guard region 36 does not have to be activated.In this case, the guard region 36 is formed as a non-semiconductorregion. The p type impurity of the guard region 36 may be activated. Inthis case, the guard region 36 is formed as a p type semiconductorregion.

The main surface insulating layer 10 described above includes a diodeopening 37 that exposes the diode region 35. The diode opening 37exposes an inner peripheral edge of the guard region 36 in addition tothe diode region 35. The diode opening 37 may be formed in aquadrilateral shape having four sides parallel to the side surfaces 5Ato 5D in plan view.

The first main surface electrode layer 12 described above enters intothe diode opening 37 from on the main surface insulating layer 10.Inside the diode opening 37, the first main surface electrode layer 12is electrically connected to the diode region 35. More specifically, thefirst main surface electrode layer 12 forms a Schottky junction with thediode region 35. The Schottky barrier diode D, having the first mainsurface electrode layer 12 as an anode and the diode region 35 as acathode, is thereby formed. The passivation layer 13 and the resin layer16 described above are formed on the main surface insulating layer 10.

FIG. 9 is a perspective view showing an SiC semiconductor wafer 41 usedin manufacturing the SiC semiconductor device 1 shown in FIG. 3.

The SiC semiconductor wafer 41 is a member to be a base of the SiCsemiconductor substrate 6. The SiC semiconductor wafer 41 includes a4H-SiC monocrystal as an example of an SiC monocrystal constituted of ahexagonal crystal. In this embodiment, the SiC semiconductor wafer 41has an n type impurity concentration corresponding to the n typeimpurity concentration of the SiC semiconductor substrate 6.

The SiC semiconductor wafer 41 is formed in a plate shape or discoidshape. The SiC semiconductor wafer 41 may be formed in a disk shape. TheSiC semiconductor wafer 41 has a first wafer main surface 42 at oneside, a second wafer main surface 43 at another side, and a wafer sidesurface 44 connecting the first wafer main surface 42 and the secondwafer main surface 43.

A thickness TW of the SiC semiconductor wafer 41 exceeds the thicknessTS of the SiC semiconductor substrate 6 (TS<TW). The thickness TW of theSiC semiconductor wafer 41 is adjusted by grinding to the thickness TSof the SiC semiconductor substrate 6.

The thickness TW may exceed 150 μm and be not more than 750 μm. Thethickness TW may exceed 150 μm and be not more than 300 μm, be not lessthan 300 μm and not more than 450 μm, be not less than 450 μm and notmore than 600 μm, or be not less than 600 μm and not more than 750 μm.In view of grinding time of the SiC semiconductor wafer 41, thethickness TW preferably exceeds 150 μm and is not more than 500 μm. Thethickness TW is typically not less than 300 μm and not more than 450 μm.

In this embodiment, the first wafer main surface 42 and the second wafermain surface 43 face the c-planes of the SiC monocrystal. The firstwafer main surface 42 faces the (0001) plane (silicon plane). The secondwafer main surface 43 faces the (000-1) plane (carbon plane) of the SiCmonocrystal.

The first wafer main surface 42 and the second wafer main surface 43have an off angle θ inclined at an angle of not more than 10° in the[11-20] direction with respect to the c-planes of the SiC monocrystal. Anormal direction Z to the first wafer main surface 42 is inclined byjust the off angle θ with respect to the c-axis ([0001] direction) ofthe SiC monocrystal.

The off angle θ may be not less than 0° and not more than 5.0°. The offangle θ may be set in an angular range of not less than 0° and not morethan 1.0°, not less than 1.0° and not more than 1.5°, not less than 1.5°and not more than 2.0°, not less than 2.0° and not more than 2.5°, notless than 2.5° and not more than 3.0°, not less than 3.0° and not morethan 3.5°, not less than 3.5° and not more than 4.0°, not less than 4.0°and not more than 4.5°, or not less than 4.5° and not more than 5.0°.The off angle θ preferably exceeds 0°. The off angle θ may be less than4.0°.

The off angle θ may be set in an angular range of not less than 3.0° andnot more than 4.5°. In this case, the off angle θ is preferably set inan angular range of not less than 3.0° and not more than 3.5°, or notless than 3.5° and not more than 4.0°. The off angle θ may be set in anangular range of not less than 1.5° and not more than 3.0°. In thiscase, the off angle θ is preferably set in an angular range of not lessthan 1.5° and not more than 2.0°, or not less than 2.0° and not morethan 2.5°.

The SiC semiconductor wafer 41 includes a first wafer corner portion 45connecting the first wafer main surface 42 and the wafer side surface44, and a second wafer corner portion 46, connecting the second wafermain surface 43 and the wafer side surface 44. The first wafer cornerportion 45 has a first chamfered portion 47 that is inclined downwardlyfrom the first wafer main surface 42 toward the wafer side surface 44.The second wafer corner portion 46 has a second chamfered portion 48that is inclined downwardly from the second wafer main surface 43 towardthe wafer side surface 44.

The first chamfered portion 47 may be formed in a convexly curved shape.The second chamfered portion 48 may be formed in a convexly curvedshape. The first chamfered portion 47 and the second chamfered portion48 suppress cracking of the SiC semiconductor wafer 41.

A orientation flat 49, as an example of a mark indicating a crystalorientation of the SiC monocrystal, is formed in the wafer side surface44. The orientation flat 49 is a notched portion formed in the waferside surface 44. In this embodiment, the orientation flat 49 extendsrectilinearly along the a-axis direction ([11-20] direction) of the SiCmonocrystal.

A plurality of (for example, two) orientation flats 49 indicating thecrystal orientations may be formed in the wafer side surface 44. Theplurality of (for example, two) orientation flats 49 may include a firstorientation flat and a second orientation flat.

The first orientation flat may be a notched portion extendingrectilinearly along the a-axis direction ([11-20] direction) of the SiCmonocrystal. The second orientation flat may be a notched portionextending rectilinearly along the m-axis direction ([1-100] direction)of the SiC monocrystal.

A plurality of device forming regions 51, each corresponding to an SiCsemiconductor device 1, are set in the first wafer main surface 42. Theplurality of device forming regions 51 are set in a matrix array atintervals in the m-axis direction ([1-100] direction) and the a-axisdirection ([11-20] direction).

Each device forming region 51 has four sides 52A, 52B, 52C, and 52Doriented along the crystal orientation of the SiC monocrystal. The foursides 52A to 52D respectively correspond to the four side surfaces 5A to5D of the SiC semiconductor layer 2. That is, the four sides 52A to 52Dinclude the two sides 52A and 52C oriented along the m-axis direction([1-100] direction) and the two sides 52B and 52D oriented along thea-axis direction ([11-20] direction).

A cutting schedule line 53 of a Lattice-shaped extending along them-axis direction ([1-100] direction) and the a-axis direction ([11-20]direction) such as to demarcate the plurality of device forming regions51 respectively is set in the first wafer main surface 42. The cuttingschedule line 53 include a plurality of first cutting schedule lines 54and a plurality of second cutting schedule lines 55.

The plurality of first cutting schedule lines 54 respectively extendalong the m-axis direction ([1-100] direction). The plurality of secondcutting schedule lines 55 respectively extend along the a-axis direction([11-20] direction). After predetermined structures are formed in theplurality of device forming regions 51, the plurality of SiCsemiconductor devices 1 are cut out by cutting the SiC semiconductorwafer 41 along the cutting schedule line 53.

FIG. 10A to FIG. 10M are sectional views of an example of a method formanufacturing the SiC semiconductor device 1 shown in FIG. 3. In FIG.10A to FIG. 10M, for convenience of description, just a region thatincludes three device forming regions 51 are shown and illustration ofother regions is omitted.

Referring to FIG. 10A, first, the SiC semiconductor wafer 41 is prepared(see also FIG. 9). Next, the SiC epitaxial layer 7 is formed on thefirst wafer main surface 42. In the step of forming the SiC epitaxiallayer 7, SiC is epitaxially grown from the first wafer main surface 42.A thickness TE of the SiC epitaxial layer 7 may be not less than 1 μmand not more than 50 μm. An SiC semiconductor wafer structure 61 thatincludes the SiC semiconductor wafer 41 and the SiC epitaxial layer 7 isthereby formed.

The SiC semiconductor wafer structure 61 includes a first main surface62 and a second main surface 63. The first main surface 62 and thesecond main surface 63 respectively correspond to the first main surface3 and the second main surface 4 of the SiC semiconductor layer 2. Athickness TWS of the SiC semiconductor wafer structure 61 may exceed 150μm and be not more than 800 μm. The thickness TWS preferably exceeds 150μm and is not more than 550 μm.

Next, referring to FIG. 10B, the p⁺ type guard regions 36 are formed inthe first main surface 62. The step of forming the guard regions 36includes a step of selectively introducing the p type impurity intosurface layer portions of the first main surface 62 via an ionimplantation mask (not shown). More specifically, the guard regions 36are formed in surface layer portions of the SiC epitaxial layer 7.

The guard regions 36 demarcate the active regions 8 and the outerregions 9 in the SiC semiconductor wafer structure 61. The n type dioderegions 35 are demarcated in regions (active regions 8) surrounded bythe guard regions 36. The diode regions 35 may be formed by selectivelyintroducing the n type impurity into surface layer portions of the firstmain surface 62 via an ion implantation mask (not shown).

Next, referring to FIG. 10C, the main surface insulating layer 10 isformed on the first main surface 62. The main surface insulating layer10 includes silicon oxide (SiO₂). The main surface insulating layer 10may be formed by a CVD (chemical vapor deposition) method or anoxidation treatment method (for example, a thermal oxidation treatmentmethod).

Next, referring to FIG. 10D, a mask 64 having a predetermined pattern isformed on the main surface insulating layer 10. The mask 64 has aplurality of openings 65. The plurality of openings 65 respectivelyexpose regions in the main surface insulating layer 10 in which thediode openings 37 are to be formed.

Next, unnecessary portions of the main surface insulating layer 10 areremoved by an etching method via the mask 64. The diode openings 37 arethereby formed in the main surface insulating layer 10. After the diodeopenings 37 are formed, the mask 64 is removed.

Next, referring to FIG. 10E, abase electrode layer 66 to be a base ofthe first main surface electrode layers 12 is formed on the first mainsurface 62. The base electrode layer 66 is formed over an entire area ofthe first main surface 62 and covers the main surface insulating layer10. The first main surface electrode layers 12 may be formed by a vapordeposition method, a sputtering method, or a plating method.

Next, referring to FIG. 10F, a mask 67 having a predetermined pattern isformed on the base electrode layer 66. The mask 67 has openings 68 thatexpose regions of the base electrode layer 66 besides regions at whichthe first main surface electrode layers 12 are to be formed.

Next, unnecessary portions of the base electrode layer 66 are removed byan etching method via the mask 67. The base electrode layer 66 isthereby divided into the plurality of first main surface electrodelayers 12. After the first main surface electrode layers 12 are formed,the mask 67 is removed.

Next, referring to FIG. 10G, the passivation layer 13 is formed on thefirst main surface 62. The passivation layer 13 includes silicon nitride(SiN). The passivation layer 13 may be formed by a CVD method.

Next, referring to FIG. 10H, the resin layer 16 is coated onto thepassivation layer 13. The resin layer 16 covers the active regions 8 andthe outer regions 9 altogether. The resin layer 16 may include apolybenzoxazole as an example of a positive type photosensitive resin.

Next, referring to FIG. 10I, the resin layer 16 is exposed selectivelyand thereafter developed. The pad openings 18 are thereby formed in theresin layer 16. Also, dicing streets 69 oriented along the cuttingschedule line 53 (the sides 52A to 52D of the respective device formingregions 51) are demarcated in the resin layer 16.

Next, unnecessary portions of the passivation layer 13 are removed. Theunnecessary portions of the passivation layer 13 may be removed by anetching method via the resin layer 16. The sub pad openings 15 arethereby formed in the passivation layer 13. Also, the dicing streets 69oriented along the cutting schedule line 53 are demarcated in thepassivation layer 13.

With this embodiment, the step of removing the unnecessary portions ofthe passivation layer 13 using the resin layer 16 was described.However, the resin layer 16 and the pad openings 18 may be formed afterforming the sub pad openings 15 in the passivation layer 13. In thiscase, before the step of forming the resin layer 16, the unnecessaryportions of the passivation layer 13 are removed by an etching methodvia a mask to form the sub pad openings 15. According to this step, thepassivation layer 13 can be formed in any shape.

Next, referring to FIG. 10J, the second main surface (second wafer mainsurface 43) is ground. The SiC semiconductor wafer structure 61 (SiCsemiconductor wafer 41) is thereby thinned. Also, grinding marks areformed in the second main surface 63 (second wafer main surface 43). TheSiC semiconductor wafer structure 61 is ground until it is of thethickness TWS corresponding to the thickness TL of the SiC semiconductorlayer 2.

The SiC semiconductor wafer structure 61 may be ground to be of thethickness TWS of not less than 40 μm and not more than 200 μm. That is,the SiC semiconductor wafer 41 is ground until it is of the thickness TWcorresponding to the thickness TS of the SiC semiconductor substrate 6.The SiC semiconductor wafer 41 may be ground to be of the thickness TWof not less than 40 μm and not more than 150 μm.

Next, referring to FIG. 10K, a plurality of modified lines 70 (modifiedlayers) to be bases of the modified lines 22A to 22D are formed. In thestep of forming the modified lines 70, pulsed laser light is irradiatedtoward the SiC semiconductor wafer structure 61 from a laser lightirradiation apparatus 71.

The laser light is irradiated onto the SiC semiconductor wafer structure61 from the first main surface 62 side and via the main surfaceinsulating layer 10. The laser light may be irradiated directly onto theSiC semiconductor wafer structure 61 from the second main surface 63side.

A light converging portion (focal point) of the laser light is set tothickness direction intermediate portions of the SiC semiconductor waferstructure 61. A laser light irradiation position with respect to the SiCsemiconductor wafer structure 61 is moved along the cutting scheduleline 53 (the four sides 52A to 52D of the respective device formingregions 51). More specifically, the laser light irradiation positionwith respect to the SiC semiconductor wafer structure 61 is moved alongthe first cutting schedule lines 54. Also, the laser light irradiationposition with respect to the SiC semiconductor wafer structure 61 ismoved along the second cutting schedule lines 55.

The plurality of modified lines 70 that extend along the cuttingschedule line 53 (the four sides 52A to 52D of the respective deviceforming regions 51) and in which a crystal state of the SiC monocrystalis modified to be of the property differing from other regions arethereby formed in the thickness direction intermediate portions of theSiC semiconductor wafer structure 61.

The plurality of modified lines 70 are formed respectively at the foursides 52A to 52D of each device forming region 51. In this embodiment,the plurality of modified lines 70 are formed in a relationship ofone-to-one correspondence with respect to the four sides 52A to 52D ofeach device forming region 51.

Each of the two modified lines 70 oriented along the sides 52A and 52Cof the device forming region 51 includes the a-plane modified portion28. Each of the two modified lines 70 oriented along the sides 52B and52D of the device forming region 51 includes the m-plane modifiedportion 29.

The plurality of modified lines 70 are also laser processing marksformed in the thickness direction intermediate portions of the SiCsemiconductor wafer structure 61. More specifically, the a-planemodified portions 28 and the m-plane modified portions 29 of themodified lines 70 are laser processing marks. The light convergingportion (focal point), laser energy, pulse duty ratio, irradiationspeed, etc., of the laser light are set to arbitrary values inaccordance with positions, sizes, shapes, thicknesses, etc., of themodified lines 70 (modified lines 22A to 22D) to be formed.

Also, in this step, a plurality of boundary modified lines 72 (boundarymodified layers) to be bases of the boundary modified lines 30A to 30Dare formed. In the step of forming the boundary modified lines 72, laserlight is irradiated toward the SiC semiconductor wafer structure 61 fromthe laser light irradiation apparatus 71. The laser light is preferablyirradiated from the first main surface 62 side. The laser light may beirradiated from the second main surface 63 side.

The light converging portion (focal point) of the laser light is set toboundary regions between the SiC semiconductor wafer structure 61 andthe main surface insulating layer 10. The laser light irradiationposition with respect to the SiC semiconductor wafer structure 61 ismoved along the cutting schedule line 53 (the four sides 52A to 52D ofthe respective device forming regions 51). More specifically, the laserlight irradiation position with respect to the SiC semiconductor waferstructure 61 is moved along the first cutting schedule lines 54. Also,the laser light irradiation position with respect to the SiCsemiconductor wafer structure 61 is moved along the second cuttingschedule lines 55.

The plurality of boundary modified lines 72 that extend along thecutting schedule line 53 (the four sides 52A to 52D of the respectivedevice forming regions 51) are thereby formed in the boundary regionsbetween the SiC semiconductor wafer structure 61 and the main surfaceinsulating layer 10. The boundary modified lines 72 include the firstregions 31 modified to be of the property differing from the SiCmonocrystal and the second regions 32 modified to be of the propertydiffering from the insulating material of the main surface insulatinglayer 10.

The plurality of boundary modified lines 72 are formed respectively atthe four sides 52A to 52D of each device forming region 51. Theplurality of boundary modified lines 72 are formed in a relationship ofone-to-one correspondence with respect to the four sides 52A to 52D ofeach device forming region 51. Each of the two boundary modified lines72 oriented along the sides 52A and 52C of the device forming region 51includes the a-plane boundary modified portion 33. Each of the twoboundary modified lines 72 oriented along the sides 52B and 52D of thedevice forming region 51 includes the m-plane boundary modified portion34.

The plurality of boundary modified lines 72 are also laser processingmarks formed in the boundary regions between the SiC semiconductor waferstructure 61 and the main surface insulating layer 10. Morespecifically, the a-plane boundary modified portions 33 and the m-planeboundary modified portions 34 of the boundary modified lines 72 arelaser processing marks. The light converging portion (focal point),laser energy, pulse duty ratio, irradiation speed, etc., of the laserlight are set to arbitrary values in accordance with positions, sizes,shapes, thicknesses, etc., of the boundary modified lines 72 (boundarymodified lines 30A to 30D) to be formed.

The boundary regions between the SiC semiconductor wafer structure 61and the main surface insulating layer 10 may be heated up to atemperature at which the insulating material of the main surfaceinsulating layer 10 melts. The boundary regions between the SiCsemiconductor wafer structure 61 and the main surface insulating layer10 may be heated up to a temperature at which the SiC monocrystal melts.In this case, the insulating material of the main surface insulatinglayer 10 also melts at the same time.

Next, referring to FIG. 10L, the second main surface electrode layer 19is formed on the second main surface 63. The second main surfaceelectrode layer 19 may be formed by a vapor deposition method, asputtering method, or a plating method. An annealing treatment may beperformed on the second main surface 63 (ground surface) before the stepof forming the second main surface electrode layer 19. The annealingtreatment may be performed by a laser annealing treatment method usinglaser light.

According to the laser annealing treatment method, the SiC monocrystalat a surface layer portion of the second main surface 63 is modified andan Si amorphous layer is formed. In this case, the SiC semiconductordevice 1 having the Si amorphous layer at a surface layer portion of thesecond main surface 4 of the SiC semiconductor layer 2 is manufactured.At the second main surface 4, the grinding marks and the Si amorphouslayer coexist. According to the laser annealing treatment method, anohmic property of the second main surface electrode layer 19 withrespect to the second main surface 4 can be improved.

Next, referring to FIG. 10M, the plurality of SiC semiconductor devices1 are cut out from the SiC semiconductor wafer structure 61. In thisstep, a tape-shaped supporting member 73 is adhered onto the second mainsurface 63 side. Next, an external force is applied to the cuttingschedule line 53 via the supporting member 73 from the second mainsurface 63 side. The external force applied to the cutting schedule line53 may be applied by a pressing member, such as a blade, etc.

The supporting member 73 may be adhered onto the first main surface 62side. In this case, the external force may be applied to the cuttingschedule line 53 via the supporting member 73 from the first mainsurface 62 side. The external force may be applied by a pressing member,such as a blade, etc.

An elastic supporting member 73 may be adhered to the first main surface62 side or the second main surface 63 side. In this case, the SiCsemiconductor wafer structure 61 may be cleaved by stretching theelastic supporting member 73 in the m-axis direction and the a-axisdirection.

If the SiC semiconductor wafer structure 61 is to be cleaved using thesupporting member 73, it is preferable to adhere the supporting member73 onto the second main surface 63 side with few obstacles. The SiCsemiconductor wafer structure 61 is thus cleaved along the cuttingschedule line 53 with the modified lines 70 and the boundary modifiedlines 72 as starting points and the plurality of SiC semiconductordevices 1 are cut out from the single SiC semiconductor wafer structure61 (SiC semiconductor wafer 41).

Portions of the modified lines 70 that are oriented along the sides 52Aof the respective device forming regions 51 become the modified lines22A. Portions of the modified lines 70 that are oriented along the sides52B of the respective device forming regions 51 become the modifiedlines 22B. Portions of the modified lines 70 that are oriented along thesides 52C of the respective device forming regions 51 become themodified lines 22C. Portions of the modified lines 70 that are orientedalong the sides 52D of the respective device forming regions 51 becomethe modified lines 22D.

Portions of the boundary modified lines 72 that are oriented along thesides 52A of the respective device forming regions 51 become theboundary modified lines 30A. Portions of the boundary modified lines 72that are oriented along the sides 52B of the respective device formingregions 51 become the boundary modified lines 30B. Portions of theboundary modified lines 72 that are oriented along the sides 52C of therespective device forming regions 51 become the boundary modified lines30C. Portions of the boundary modified lines 72 that are oriented alongthe sides 52D of the respective device forming regions 51 become theboundary modified lines 30D. The SiC semiconductor devices 1 aremanufactured through steps including the above.

In this embodiment, the step of grinding the SiC semiconductor waferstructure 61 (FIG. 10J) is performed before the step of forming themodified lines 70 and the boundary modified lines 72 (FIG. 10K).However, the step of grinding the SiC semiconductor wafer structure 61(FIG. 10J) may be performed at any timing after the step of preparingthe SiC semiconductor wafer 41 (FIG. 10A) and before the step of formingthe second main surface electrode layer 19 (FIG. 10L).

For example, the step of grinding the SiC semiconductor wafer structure61 (FIG. 10J) may be performed before the step of forming the SiCepitaxial layer 7 (FIG. 10A). Also, the step of grinding the SiCsemiconductor wafer structure 61 (FIG. 10J) may be performed after thestep of forming the modified lines 70 and the boundary modified lines 72(FIG. 10K).

Also, the step of grinding the SiC semiconductor wafer structure 61(FIG. 10J) may be performed over a plurality of times at any timingafter the step of preparing the SiC semiconductor wafer 41 (FIG. 10A)and before the step of forming the modified lines 70 and the boundarymodified lines 72 (FIG. 10K). Also, the step of grinding the SiCsemiconductor wafer structure 61 (FIG. 10J) may be performed over aplurality of times at any timing after the step of preparing the SiCsemiconductor wafer 41 (FIG. 10A) and before the step of forming thesecond main surface electrode layer 19 (FIG. 10L).

FIG. 11 is a perspective view, as seen through a sealing resin 79, of asemiconductor package 74 incorporating the SiC semiconductor device 1shown in FIG. 3.

Referring to FIG. 11, the semiconductor package 74 in this embodiment isof a so-called TO-220 type. The semiconductor package 74 includes theSiC semiconductor device 1, a pad portion 75, a heat sink 76, aplurality of (in this embodiment, two) terminals 77, a plurality of (inthis embodiment, two) conductive wires 78, and a sealing resin 79. Thepad portion 75, the heat sink 76, and the plurality of terminals 77 forma lead frame as an example of a connection object.

The pad portion 75 includes a metal plate. The pad portion 75 mayinclude iron, gold, silver, copper, aluminum, etc. The pad portion 75 isformed in a quadrilateral shape in plan view. The pad portion 75 has aplane area not less than a plane area of the SiC semiconductor device 1.The SiC semiconductor device 1 is arranged on the pad portion 75.

The second main surface electrode layer 19 of the SiC semiconductordevice 1 is electrically connected to the pad portion 75 via aconductive bonding material 80. The conductive bonding material 80 isinterposed in a region between the second main surface electrode layer19 and the pad portion 75.

The conductive bonding material 80 may be a metal paste or a solder. Themetal paste may be a conductive paste including Au (gold), Ag (silver),or Cu (copper). The conductive bonding material 80 is preferablyconstituted of the solder. The solder may be a lead-free type solder.The solder may include at least one type of material among SnAgCu,SnZnBi, SnCu, SnCuNi, and SnSbNi.

The heat sink 76 is connected to one side of the pad portion 75. In thisembodiment, the pad portion 75 and the heat sink 76 are formed of asingle metal plate. A penetrating hole 76 a is formed in the heat sink76. The penetrating hole 76 a is formed in a circular shape.

The plurality of terminals 77 are aligned along a side opposite the heatsink 76 with respect to the pad portion 75. The plurality of terminals77 includes a metal plate respectively. The terminals 77 may includeiron, gold, silver, copper, aluminum, etc.

The plurality of terminals 77 include a first terminal 77A and a secondterminal 77B. The first terminal 77A and the second terminal 77B arealigned at an interval along a side of the pad portion 75 opposite theheat sink 76. The first terminal 77A and the second terminal 77B extendin band shapes along a direction orthogonal to a direction of alignmentthereof.

The plurality of conductive wires 78 may be bonding wires, etc. Theplurality of conductive wires 78 include a conductive wire 78A and aconductive wire 78B. The conductive wire 78A is electrically connectedto the first terminal 77A and the first main surface electrode layer 12of the SiC semiconductor device 1. The first terminal 77A is therebyelectrically connected to the first main surface electrode layer 12 ofthe SiC semiconductor device 1 via the conductive wire 78A.

The conductive wire 78B is electrically connected to the second terminal77B and the pad portion 75. The second terminal 77B is therebyelectrically connected to the second main surface electrode layer 19 ofthe SiC semiconductor device 1 via the conductive wire 78B. The secondterminal 77B may be formed integral to the pad portion 75.

The sealing resin 79 seals the SiC semiconductor device 1, the padportion 75, and the plurality of conductive wires 78 such as to exposethe heat sink 76 and portions of the plurality of terminals 77. Thesealing resin 79 is formed in a rectangular parallelepiped shape.

The configuration of the semiconductor package 74 is not restricted toTO-220. A SOP (small outline package), a QFN (quad for non-leadpackage), a DFP (dual flat package), a DIP (dual inline package), a QFP(quad flat package), a SIP (single inline package), a SOJ (small outlineJ-leaded package), or any of various similar configurations may beapplied as the semiconductor package 74.

As described above, the SiC semiconductor device 1 includes the boundarymodified lines 30A to 30D formed across the side surfaces 5A to 5D ofthe SiC semiconductor layer 2 and the insulating side surfaces 11A to11D of the main surface insulating layer 10. The boundary modified lines30A to 30D include the first regions 31 modified to be of the propertydiffering from the SiC monocrystal and the second regions 32 modified tobe of the property differing from the insulating material of the mainsurface insulating layer 10.

In the method for manufacturing the SiC semiconductor device 1, the SiCsemiconductor wafer structure 61 is cleaved with the boundary modifiedlines 30A to 30D, formed across the SiC semiconductor wafer structure 61and the main surface insulating layer 10, as cleaving starting points(cutting starting points). Lowering of adhesion force of the mainsurface insulating layer 10 and peeling of the main surface insulatinglayer 10 due to impact during cleaving (during cutting) of the SiCsemiconductor wafer structure 61 can thus be suppressed. Consequently,the SiC semiconductor device 1 in which the peeling of the main surfaceinsulating layer 10 can be suppressed can be provided.

The SiC semiconductor device 1 preferably includes the fixing layer thatfixes the side surfaces 5A to 5D and the insulating side surfaces 11A to11D. According to the fixing layer, peeling of the main surfaceinsulating layer 10 can be suppressed appropriately. The fixing layermay include the weld layer welded to the side surfaces 5A to 5D and theinsulating side surfaces 11A to 11D. The fixing layer may include theinsulating weld portion in which the insulating material melted from themain surface insulating layer 10 is welded to the side surfaces 5A to5D. The fixing layer may include the SiC weld portion in which the SiCmonocrystal melted from the SiC semiconductor layer 2 is welded to theinsulating side surfaces 11A to 11D. The fixing layer may include boththe insulating weld portion and the SiC weld portion.

The fixing layer may be formed by the first regions 31 and the secondregions 32 of the boundary modified lines 30A to 30D. The fixing layermay be formed by the a-plane boundary modified portions 33 and them-plane boundary modified portions 34. The fixing layer may include aportion or all of the boundary modified lines 30A to 30D.

Also, with the SiC semiconductor device 1, the step of thinning the SiCsemiconductor wafer structure 61 (SiC semiconductor wafer 41) isperformed and therefore the SiC semiconductor wafer structure 61 can becleaved appropriately by a single layer of the modified lines 70(modified lines 22A to 22D). In other words, according to the thinnedSiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), theSiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can becleaved appropriately without forming a plurality of the modified lines70 (modified lines 22A to 22D) at intervals in the normal direction Z.

In this case, the second main surface 4 of the SiC semiconductor layer 2is constituted of the ground surface. The SiC semiconductor device 1preferably includes the SiC semiconductor layer 2 having the thicknessTL that is not less than 40 μm and not more than 200 μm. The SiCsemiconductor layer 2 having such thickness TL can be cut outappropriately from the SiC semiconductor wafer structure 61 (SiCsemiconductor wafer 41).

In the SiC semiconductor layer 2, the thickness TS of the SiCsemiconductor substrate 6 may be not less than 40 μm and not more than150 μm. The thickness TE of the SiC epitaxial layer 7 in the SiCsemiconductor layer 2 may be not less than 1 μm and not more than 50 μm.The thinning of the SiC semiconductor layer 2 is also effective in termsof reducing resistance value.

Also, according to the SiC semiconductor device 1, the main surfaceinsulating layer 10 and the first main surface electrode layer 12 formedon the first main surface 3 are included. The main surface insulatinglayer 10 has the insulating side surfaces 11A to 11D that are continuousto the side surfaces 5A to 5D.

The main surface insulating layer 10 improves an insulating propertybetween the side surfaces 5A to 5D and the first main surface electrodelayer 12 in the structure in which the modified lines 22A to 22D areformed. Stability of electrical characteristics of the SiC semiconductorlayer 2 can thereby be improved in the structure in which the modifiedlines 22A to 22D and the boundary modified lines 30A to 30D are formed.

FIG. 12A is a perspective view showing the SiC semiconductor device 1shown in FIG. 3 and is a perspective view showing a second configurationexample of the modified lines 22A to 22D. In the following, structurescorresponding to structures described with the SiC semiconductor device1 shall be provided with the same reference signs and descriptionthereof shall be omitted.

The modified lines 22A to 22D according to the first configurationexample are continuous to each other at the corner portions connectingthe side surfaces 5A to 5D. On the other hand, the modified lines 22A to22D according to the second configuration example are formed atintervals from each other at the corner portions connecting the sidesurfaces 5A to 5D.

The modified line 22A and the modified line 22B are formed at aninterval from each other in the normal direction Z at the corner portionconnecting the side surface 5A and the side surface 5B. The modifiedline 22B and the modified line 22C are formed at an interval from eachother in the normal direction Z at the corner portion connecting theside surface 5B and the side surface 5C.

The modified line 22C and the modified line 22D are formed at aninterval from each other in the normal direction Z at the corner portionconnecting the side surface 5C and the side surface 5D. The modifiedline 22D and the modified line 22A are formed at an interval from eachother in the normal direction Z at the corner portion connecting theside surface 5D and the side surface 5A.

Obviously, at least one of the modified lines 22A to 22D may be formedat an interval from the others of the modified lines 22A to 22D at acorner portion connecting any of the side surfaces 5A to 5D. Two orthree of the modified lines 22A to 22D may be continuous to each otherat a corner portion or corner portions connecting any of the sidesurfaces 5A to 5D.

The modified lines 22A to 22D according to the second configurationexample are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K). Even in a case where the modified lines22A to 22D according to the second configuration example are formed, thesame effects as in the case of forming the modified lines 22A to 22Daccording to the first configuration example can be exhibited.

FIG. 12B is a perspective view showing the SiC semiconductor device 1shown in FIG. 3 and is a perspective view showing a third configurationexample of the modified lines 22A to 22D. In the following, structurescorresponding to the structures described with the SiC semiconductordevice shall be provided with the same reference signs and descriptionthereof shall be omitted.

The modified lines 22A to 22D according to the first configurationexample are formed in band shapes extending rectilinearly along thetangential directions to the first main surface 3. On the other hand,the modified lines 22A to 22D according to the third configurationexample are formed in band shapes extending in slope shapes incliningdownwardly from the first main surface 3 toward the second main surface4. More specifically, the modified lines 22A to 22D according to thethird configuration example each include a first end portion region 81,a second end portion region 82, and a slope region 83.

The first end portion regions 81 are positioned at the first mainsurface 3 side in vicinities of the corner portions of the SiCsemiconductor layer 2. The second end portion regions 82 are positionedat the second main surface 4 sides with respect to the first end portionregions 81 in the vicinities of the corner portions of the SiCsemiconductor layer 2. The slope regions 83 are inclined downwardly fromthe first main surface 3 toward the second main surface 4 in regionsbetween the first end portion regions 81 and the second end portionregions 82.

The first end portion region 81 of the modified line 22A and the firstend portion region 81 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.The second end portion region 82 of the modified line 22A and the secondend portion region 82 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.

The first end portion region 81 of the modified line 22A and the secondend portion region 82 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.The second end portion region 82 of the modified line 22A and the firstend portion region 81 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.The modified line 22A and the modified line 22B may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5A and the side surface 5B.

The first end portion region 81 of the modified line 22B and the firstend portion region 81 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.The second end portion region 82 of the modified line 22B and the secondend portion region 82 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.

The first end portion region 81 of the modified line 22B and the secondend portion region 82 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.The second end portion region 82 of the modified line 22B and the firstend portion region 81 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.The modified line 22B and the modified line 22C may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5B and the side surface 5C.

The first end portion region 81 of the modified line 22C and the firstend portion region 81 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.The second end portion region 82 of the modified line 22C and the secondend portion region 82 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.

The first end portion region 81 of the modified line 22C and the secondend portion region 82 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.The second end portion region 82 of the modified line 22C and the firstend portion region 81 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.The modified line 22C and the modified line 22D may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5C and the side surface 5D.

The first end portion region 81 of the modified line 22D and the firstend portion region 81 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.The second end portion region 82 of the modified line 22D and the secondend portion region 82 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.

The first end portion region 81 of the modified line 22D and the secondend portion region 82 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.The second end portion region 82 of the modified line 22D and the firstend portion region 81 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.The modified line 22D and the modified line 22A may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5D and the side surface 5A.

The modified lines 22A to 22D according to the third configurationexample are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K). Even in a case where the modified lines22A to 22D according to the third configuration example are formed, thesame effects as in the case of forming the modified lines 22A to 22Daccording to the first configuration example can be exhibited.

In particular with the modified lines 22A to 22D according to the thirdconfiguration example, the cleaving starting points can be formed indifferent regions in a thickness direction of the SiC semiconductorwafer structure 61 (SiC semiconductor wafer 41). The SiC semiconductorwafer structure 61 can thereby be cleaved appropriately even when themodified lines 22A to 22D constituted of a single layer are formed.

FIG. 12C is a perspective view showing the SiC semiconductor device 1shown in FIG. 3 and is a perspective view showing a fourth configurationexample of the modified lines 22A to 22D. In the following, structurescorresponding to the structures described with the SiC semiconductordevice shall be provided with the same reference signs and descriptionthereof shall be omitted.

The modified lines 22A to 22D according to the first configurationexample are formed in band shapes extending rectilinearly along thetangential directions to the first main surface 3. On the other hand,the modified lines 22A to 22D according to the fourth configurationexample are formed in band shapes extending such as to be inclineddownwardly in curves (curved shapes) from the first main surface 3toward the second main surface 4. More specifically, the modified lines22A to 22D according to the fourth configuration example each include afirst end portion region 84, a second end portion region 85, and acurved region 86.

The first end portion regions 84 are positioned at the first mainsurface 3 side in vicinities of the corner portions of the SiCsemiconductor layer 2. The second end portion regions 85 are positionedat the second main surface 4 side with respect to the first end portionregions 84 in the vicinities of the corner portions of the SiCsemiconductor layer 2. The curved regions 86 are inclined downwardlyfrom the first main surface 3 toward the second main surface 4 inconcavely curved shapes and connect the first end portion regions 84 andthe second end portion regions 85. The curved regions 86 may be inclineddownwardly from the first main surface 3 toward the second main surface4 in convexly curved shapes.

The first end portion region 84 of the modified line 22A and the firstend portion region 84 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.The second end portion region 85 of the modified line 22A and the secondend portion region 85 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.

The first end portion region 84 of the modified line 22A and the secondend portion region 85 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.The second end portion region 85 of the modified line 22A and the firstend portion region 84 of the modified line 22B may be positioned at thecorner portion connecting the side surface 5A and the side surface 5B.The modified line 22A and the modified line 22B may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5A and the side surface 5B.

The first end portion region 84 of the modified line 22B and the firstend portion region 84 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.The second end portion region 85 of the modified line 22B and the secondend portion region 85 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.

The first end portion region 84 of the modified line 22B and the secondend portion region 85 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.The second end portion region 85 of the modified line 22B and the firstend portion region 84 of the modified line 22C may be positioned at thecorner portion connecting the side surface 5B and the side surface 5C.The modified line 22B and the modified line 22C may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5B and the side surface 5C.

The first end portion region 84 of the modified line 22C and the firstend portion region 84 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.The second end portion region 85 of the modified line 22C and the secondend portion region 85 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.

The first end portion region 84 of the modified line 22C and the secondend portion region 85 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.The second end portion region 85 of the modified line 22C and the firstend portion region 84 of the modified line 22D may be positioned at thecorner portion connecting the side surface 5C and the side surface 5D.The modified line 22C and the modified line 22D may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5C and the side surface 5D.

The first end portion region 84 of the modified line 22D and the firstend portion region 84 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.The second end portion region 85 of the modified line 22D and the secondend portion region 85 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.

The first end portion region 84 of the modified line 22D and the secondend portion region 85 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.The second end portion region 85 of the modified line 22D and the firstend portion region 84 of the modified line 22A may be positioned at thecorner portion connecting the side surface 5D and the side surface 5A.The modified line 22D and the modified line 22A may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5D and the side surface 5A.

The modified lines 22A to 22D according to the fourth configurationexample are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K). Even in a case where the modified lines22A to 22D according to the fourth configuration example are formed, thesame effects as in the case of forming the modified lines 22A to 22Daccording to the first configuration example can be exhibited.

In particular with the modified lines 22A to 22D according to the fourthconfiguration example, the cleaving starting points can be formed indifferent regions in the thickness direction of the SiC semiconductorwafer structure 61 (SiC semiconductor wafer 41). The SiC semiconductorwafer structure 61 can thereby be cleaved appropriately even when themodified lines 22A to 22D constituted of a single layer are formed.

FIG. 12D is a perspective view showing the SiC semiconductor device 1shown in FIG. 3 and is a perspective view showing a fifth configurationexample of the modified lines 22A to 22D. In the following, structurescorresponding to the structures described with the SiC semiconductordevice shall be provided with the same reference signs and descriptionthereof shall be omitted.

The modified lines 22A to 22D according to the first configurationexample are formed in band shapes extending rectilinearly along thetangential directions to the first main surface 3. On the other hand,the modified lines 22A to 22D according to the fifth configurationexample are formed in band shapes extending in curves (curved shapes)meandering from the first main surface 3 toward the second main surface4. More specifically, the modified lines 22A to 22D according to thefifth configuration example each include a plurality of first regions87, a plurality of second regions 88, and a plurality of connectingregions 89.

The plurality of first regions 87 are positioned at regions at the firstmain surface 3 side. The plurality of second regions 88 are positionedat the second main surface 4 side with respect to the plurality of firstregions 87. The plurality of curved regions 86 connects thecorresponding first region 87 and second region 88 respectively.

The modified line 22A and the modified line 22B may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5A and the side surface 5B. Themodified line 22B and the modified line 22C may be continuous to eachother or may be formed at an interval from each other at the cornerportion connecting the side surface 5B and the side surface 5C.

The modified line 22C and the modified line 22D may be continuous toeach other or may be formed at an interval from each other at the cornerportion connecting the side surface 5C and the side surface 5D. Themodified line 22D and the modified line 22A may be continuous to eachother or may be formed at an interval from each other at the cornerportion connecting the side surface 5D and the side surface 5A.

Meandering cycles of the modified lines 22A to 22D are arbitrary. Themodified lines 22A to 22D may each be formed in a single band shapeextending in a concavely curved shape from the first main surface 3toward the second main surface 4. In this case, each of the modifiedlines 22A to 22D may include two first regions 87, one second region 88,and two connecting regions 89.

Also, the modified lines 22A to 22D may each be formed in a single bandshape extending in a convexly curved shape from the second main surface4 toward the first main surface 3. In this case, each of the modifiedlines 22A to 22D may include one first region 87, two second regions 88,and two connecting regions 89.

The modified lines 22A to 22D according to the fifth configurationexample are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K). Even in a case where the modified lines22A to 22D according to the fifth configuration example are formed, thesame effects as in the case of forming the modified lines 22A to 22Daccording to the first configuration example can be exhibited.

In particular with the modified lines 22A to 22D according to the fifthconfiguration example, the cleaving starting points can be formed indifferent regions in the thickness direction of the SiC semiconductorwafer structure 61 (SiC semiconductor wafer 41). The SiC semiconductorwafer structure 61 can thereby be cleaved appropriately even when themodified lines 22A to 22D constituted of a single layer are formed.

FIG. 12E is a perspective view showing the SiC semiconductor device 1shown in FIG. 3 and is a perspective view showing a sixth configurationexample of the modified lines 22A to 22D. In the following, structurescorresponding to the structures described with the SiC semiconductordevice 1 shall be provided with the same reference signs and descriptionthereof shall be omitted.

The modified lines 22A to 22D according to the first configurationexample are formed in equal shapes at the side surfaces 5A to 5D. On theother hand, the modified lines 22A to 22D according to the sixthconfiguration example are formed at different occupying ratios RA, RB,RC, and RD at the side surfaces 5A to 5D. The occupying ratios RA to RDare ratios of the modified lines 22A to 22D occupying in the sidesurfaces 5A to 5D.

For this configuration, an example is shown where two layers each of themodified lines 22A and 22C are formed at the side surfaces 5A and 5Crespectively, and one layer each of the modified lines 22B and 22D areformed at the side surfaces 5B and 5D respectively. One each of themodified lines 22A to 22D may be formed at a thickness directionintermediate portion of the SiC semiconductor layer 2 at each of theside surfaces 5A to 5D in a relationship of one-to-one correspondence.

More specifically, the occupying ratios RA to RD differ in accordancewith the crystal planes of the SiC monocrystal. The occupying ratios RBand RD of the modified lines 22B and 22D formed at the m-planes of theSiC monocrystal are not more than the occupying ratios RA and RC of themodified lines 22A and 22C formed at the a-planes of the SiC monocrystal(RB, RD≤RA, RC). More specifically, the occupying ratios RB and RD areless than occupying ratios RA and RC (RB, RD<RA, RC).

The occupying ratios RA and RC of the modified lines 22A and 22C may bemutually equal or may be mutually different. The occupying ratios RB andRD of the modified lines 22B and 22D may be mutually equal or may bemutually different.

In this configuration, surface areas of the modified lines 22B and 22Dwith respect to the side surfaces 5B and 5D are less than surface areasof the modified lines 22A and 22C with respect to the side surfaces 5Aand 5C. In this configuration, the thicknesses TR of the modified lines22B and 22D are less than the thicknesses TR of the modified lines 22Aand 22C.

The modified lines 22A to 22D according to the sixth configurationexample are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K). Even in a case where the modified lines22A to 22D according to the sixth configuration example are formed, thesame effects as in the case of forming the modified lines 22A to 22Daccording to the first configuration example can be exhibited.

In particular, the modified lines 22A to 22D according to the sixthconfiguration example are respectively formed at the different occupyingratios RA to RD at the side surfaces 5A to 5D. More specifically, themodified lines 22A to 22D have occupying ratios RA to RD that differ inaccordance with the crystal planes of the SiC monocrystal. The occupyingratios RB and RD of the modified lines 22B and 22D formed at them-planes of the SiC monocrystal are not more than the occupying ratiosRA and RC of the modified lines 22A and 22C formed at the a-planes ofthe SiC monocrystal (RB, RD≤RA, RC).

In a plan view of viewing the c-plane (silicon plane) from the c-axis,the SiC monocrystal has a physical property of cracking easily along thenearest atom directions (see also FIG. 1 and FIG. 2) and not crackingeasily along directions intersecting the nearest atom directions. Thenearest atom directions are the a-axis direction and directionsequivalent thereto. The crystal planes oriented along the nearest atomdirections are the m-planes and planes equivalent thereto. Thedirections intersecting the nearest atom directions are the m-axisdirection and directions equivalent thereto. The crystal planes orientedalong the directions intersecting the nearest atom directions are thea-planes and planes equivalent thereto.

Therefore, even if, in the step of forming the modified lines 70, themodified lines 70 having comparatively large occupying ratios are notformed at the crystal planes oriented along the nearest atom directionsof the SiC monocrystal, the SiC monocrystal can be cut (cleaved)appropriately because these crystal planes have the property of crackingcomparatively easily (see also FIG. 10L).

That is, in the step of forming the modified lines 70, the occupyingratios of the modified lines 70 oriented along the second cuttingschedule lines 55 extending in the a-axis direction can be made smallerthan the occupying ratios of the modified lines 70 oriented along thefirst cutting schedule lines 54 extending in the m-axis direction.

On the other hand, the modified lines 70 having the comparatively largeoccupying ratios are formed at the crystal planes oriented along thedirections intersecting the nearest atom directions of the SiCmonocrystal. Inappropriate cutting (cleaving) of the SiC semiconductorwafer structure 61 can thereby be suppressed and generation of cracksdue to the physical property of the SiC monocrystal can thus besuppressed appropriately.

Thus, with the modified lines 22A to 22D according to the sixthconfiguration example, the physical property of the SiC monocrystal canbe used to adjust and reduce the occupying ratios RA to RD with respectto the side surfaces 5A to 5D. Time reduction of the step of forming themodified lines 70 can thus be achieved.

The occupying ratios RA to RD may be adjusted by the surface areas ofthe modified lines 22A to 22D with respect to the side surfaces 5A to5D. The occupying ratios RA to RD may be adjusted by the thicknesses TRof the modified lines 22A to 22D. The occupying ratios RA to RD may beadjusted by the numbers of the modified lines 22A to 22D.

FIG. 12F is a perspective view showing the SiC semiconductor device 1shown in FIG. 3 and is a perspective view showing a seventhconfiguration example of the modified lines 22A to 22D. In thefollowing, structures corresponding to the structures described with theSiC semiconductor device shall be provided with the same reference signsand description thereof shall be omitted.

The modified lines 22A to 22D according to the first configurationexample are formed at intervals from the first main surface 3 and thesecond main surface 4 at the side surfaces 5A to 5D. On the other hand,the modified lines 22A to 22D according to the seventh configurationexample are formed over entire areas of the side surfaces 5A to 5D.

More specifically, a plurality (in this configuration, six layers) ofthe modified lines 22A, a plurality (in this configuration, six layers)of the modified lines 22B, a plurality (in this configuration, sixlayers) of the modified lines 22C, and a plurality (in thisconfiguration, six layers) of the modified lines 22D are formed over theentire areas of the side surfaces 5A to 5D.

The plurality of modified lines 22A are formed shifted from each otherin the normal direction Z. The plurality of modified lines 22A areformed at intervals from each other in the normal direction Z. Theplurality of modified lines 22A may be mutually overlapped in the normaldirection Z. The modified line 22A nearest the first main surface 3 isoverlapped with the border modified line 30A.

The plurality of modified lines 22B are formed shifted from each otherin the normal direction Z. The plurality of modified lines 22B areformed at intervals from each other in the normal direction Z. Theplurality of modified lines 22B may be mutually overlapped in the normaldirection Z. The modified line 22B nearest the first main surface 3 isoverlapped with the border modified line 30B.

The plurality of modified lines 22C are formed shifted from each otherin the normal direction Z. The plurality of modified lines 22C areformed at intervals from each other in the normal direction Z. Theplurality of modified lines 22C may be mutually overlapped in the normaldirection Z. The modified line 22C nearest the first main surface 3 isoverlapped with the border modified line 30C.

The plurality of modified lines 22D are formed shifted from each otherin the normal direction Z. The plurality of modified lines 22D areformed at intervals from each other in the normal direction Z. Theplurality of modified lines 22D may be mutually overlapped in the normaldirection Z. The modified line 22D nearest the first main surface 3 isoverlapped with the border modified line 30D.

The modified lines 22A to 22D according to the seventh configurationexample are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K). Even in a case where the modified lines22A to 22D according to the seventh configuration example are formed,the same effects as in the case of forming the modified lines 22A to 22Daccording to the first configuration example can be exhibited.

With this configuration example, an example where the plurality ofmodified lines 22A to 22D are respectively formed over the entire areasof the side surfaces 5A to 5D was described. However, modified lines 22Ato 22D, each constituted of one layer, may be respectively formed overthe entire areas of the side surfaces 5A to 5D. Such modified lines 22Ato 22D are formed by adjusting the light converging portion (focalpoint), etc., of the laser light in the step of forming the modifiedlines 70 (see also FIG. 10K).

Also, boundary modified lines 30A to 30D that are each constituted ofone layer and serve in common as the modified lines 22A to 22D may beformed over the entire areas of the side surfaces 5A to 5D and at theinsulating side surfaces 11A to 11D. Such boundary modified lines 30A to30D are formed by adjusting the light converging portion (focal point),etc., of the laser light in the step of forming the modified lines 70(see also FIG. 10K).

The SiC semiconductor device 1 that includes at least two types of themodified lines 22A to 22D according to the first configuration example,second configuration example, third configuration example, fourthconfiguration example, fifth configuration example, sixth configurationexample, and seventh configuration example (hereinafter referred tosimply as the “first to seventh configuration examples”) at the sametime may be formed.

Features of the modified lines 22A to 22D according to the first toseventh configuration examples may be combined among each other in anymode or any configuration. That is, the modified lines 22A to 22D havingconfigurations combining at least two features among the features of themodified lines 22A to 22D according to the first to seventhconfiguration examples may be adopted.

For example, the features of the modified lines 22A to 22D according tothe third configuration example may be combined with the features of themodified lines 22A to 22D according to the fifth configuration example.In this case, band shaped modified lines 22A to 22D inclined downwardlyfrom the first main surface 3 toward the second main surface 4 andextending in curves (curved shapes) meandering from the first mainsurface 3 toward the second main surface 4 are formed.

FIG. 13 is a perspective view showing an SiC semiconductor device 91according to a second preferred embodiment of the present invention andis a perspective view showing a structure applied with the modifiedlines 22A to 22D according to the first configuration example. FIG. 14is an enlarged view of a region XIV shown in FIG. 13. FIG. 15 is anenlarged view of a region XV shown in FIG. 13. In the following,structures corresponding to the structures described with the SiCsemiconductor device 1 shall be provided with the same reference signsand description thereof shall be omitted.

In this embodiment, the modified lines 22A to 22D according to the firstconfiguration example are applied. However, any one of the modifiedlines 22A to 22D according to the second to seventh configurationexamples may be adopted in place of or in addition to the modified lines22A to 22D according to the first configuration example. Also, themodified lines 22A to 22D having configurations combining at least twofeatures among the features of the modified lines 22A to 22D accordingto the first to seventh configuration examples may be adopted.

Referring to FIG. 13 to FIG. 15, in this embodiment, the side surfaces14A to 14D of the passivation layer 13 are continuous to the insulatingside surfaces 11A to 11D of the main surface insulating layer 10. Thatis, the side surfaces 5A to 5D, the insulating side surfaces 11A to 11D,and the side surfaces 14A to 14D are formed flush with each other.

In this embodiment, the boundary modified lines 30A to 30D include thirdregions 92 formed at the side surfaces 14A to 14D of the passivationlayer 13. The third regions 92 of the boundary modified lines 30A to 30Dinclude regions that are modified to be of a property differing indensity, refractive index, mechanical strength (crystal strength), orother physical characteristic from the insulating material of thepassivation layer 13. The third regions 92 of the boundary modifiedlines 30A to 30D may include at least one layer among amelted-and-rehardened layer, a defect layer, a dielectric breakdownlayer, and a refractive index change layer.

The melted-and-rehardened layer is a layer in which a portion of thepassivation layer 13 is melted and thereafter hardened again. The defectlayer is a layer that includes a hole, fissure, etc., formed in thepassivation layer 13. The dielectric breakdown layer is a layer in whicha portion of the passivation layer 13 has undergone dielectricbreakdown. The refractive index change layer is a layer in which aportion of the passivation layer 13 is changed to a refractive indexdiffering from the insulating material of the passivation layer 13.

The third regions 92 of the boundary modified lines 30A to 30D areformed at intervals toward the SiC semiconductor layer 2 side from amain surface of the passivation layer 13. The third regions 92 therebyexpose surface layer portions of the main surface of the passivationlayer 13 from the side surfaces 14A to 14D. The boundary modified lines30A to 30D may be formed over entire areas of the side surfaces 14A to14D.

The third region 92 of the boundary modified line 30A and the thirdregion 92 of the boundary modified line 30B are continuous to each otherat a corner portion connecting the side surface 14A and the side surface14B. The third region 92 of the boundary modified line 30B and the thirdregion 92 of the boundary modified line 30C are continuous to each otherat a corner portion connecting the side surface 14B and the side surface14C.

The third region 92 of the boundary modified line 30C and the thirdregion 92 of the boundary modified line 30D are continuous to each otherat a corner portion connecting the side surface 14C and the side surface14D. The third region 92 of the boundary modified line 30D and the thirdregion 92 of the boundary modified line 30A are continuous to each otherat the corner portion connecting the side surface 14D and the sidesurface 14A.

The third regions 92 of the boundary modified lines 30A to 30D arethereby formed integrally such as to surround the passivation layer 13.That is, the third regions 92 of the boundary modified lines 30A to 30Dform a single endless (annular) boundary modified line surrounding thepassivation layer 13 at the side surfaces 14A to 14D of the passivationlayer 13.

In the boundary modified lines 30A and 30C, the one end portions 33 a ofthe a-plane boundary modified portions 33 are positioned at the SiCsemiconductor layer 2. Also, the other end portions 33 b of the a-planeboundary modified portions 33 are positioned at the passivation layer13. Also, the connection portions 33 c of the a-plane boundary modifiedportions 33 cross boundary regions between the main surface insulatinglayer 10 and the passivation layer 13 and the boundary regions betweenthe SiC semiconductor layer 2 and the main surface insulating layer 10to connect the first end portions 33 a and the other end portions 33 b.

In the boundary modified lines 30B and 30D, the one end portions 34 a ofthe m-plane boundary modified portions 34 are positioned at the SiCsemiconductor layer 2. Also, the other end portions 34 b of the m-planeboundary modified portions 34 are positioned at the passivation layer13. Also, the connection portions 34 c of the m-plane boundary modifiedportions 34 cross boundary regions between the main surface insulatinglayer 10 and the passivation layer 13 and the boundary regions betweenthe SiC semiconductor layer 2 and the main surface insulating layer 10to connect the first end portions 34 a and the other end portions 34 b.

The passivation layer 13 is formed by eliminating the step of removingthe passivation layer 13 in the step of FIG. 10I described above. Also,the boundary modified lines 30A to 30D are formed by adjusting the lightconverging portion (focal point), etc., of the laser light in the stepof forming the boundary modified lines 72 (see also FIG. 10K).

As described above, even with the SiC semiconductor device 91, the sameeffects as the effects described for the SiC semiconductor device 1 canbe exhibited.

FIG. 16 is a perspective view as viewed from one angle of an SiCsemiconductor device 101 according to a third preferred embodiment ofthe present invention and is a perspective view showing a structureapplied with the modified lines 22A to 22D according to the firstconfiguration example. FIG. 17 is a perspective view as viewed fromanother angle of the SiC semiconductor device 101 shown in FIG. 16. FIG.18 is a plan view of the SiC semiconductor device 101 shown in FIG. 16.FIG. 19 is a plan view with a resin layer 129 removed from FIG. 18.

In this embodiment, the modified lines 22A to 22D according to the firstconfiguration example are applied. That is, in a manufacturing processof the SiC semiconductor device 101, the same steps as the steps of FIG.10A to FIG. 10M described above are applied.

In the SiC semiconductor device 101, any one of the modified lines 22Ato 22D according to the second to seventh configuration examples may beadopted in place of or in addition to the modified lines 22A to 22Daccording to the first configuration example. Also, the modified lines22A to 22D having configurations combining at least two features amongthe features of the modified lines 22A to 22D according to the first toseventh configuration examples may be adopted.

Referring to FIG. 16 to FIG. 19, the SiC semiconductor device 101includes an SiC semiconductor layer 102. The SiC semiconductor layer 102includes a 4H-SiC monocrystal as an example of an SiC monocrystalconstituted of a hexagonal crystal. The SiC semiconductor layer 102 isformed in a chip shape of rectangular parallelepiped shape.

The SiC semiconductor layer 102 has a first main surface 103 at oneside, a second main surface 104 at another side, and side surfaces 105A,105B, 105C, and 105D connecting the first main surface 103 and thesecond main surface 104. The first main surface 103 and the second mainsurface 104 are formed in quadrilateral shapes (rectangular shapes here)in a plan view as viewed in a normal direction Z thereof (hereinafterreferred to simply as “plan view”).

The first main surface 103 is a device surface in which a functionaldevice is formed. The second main surface 104 is constituted of a groundsurface having grinding marks. The side surfaces 105A to 105D are eachconstituted of a smooth cleavage surface facing a crystal plane of theSiC monocrystal. The side surfaces 105A to 105D are free from a grindingmark.

A thickness TL of the SiC semiconductor layer 102 may be not less than40 μm and not more than 200 μm. The thickness TL may be not less than 40μm and not more than 60 μm, not less than 60 μm and not more than 80 μm,not less than 80 μm and not more than 100 μm, not less than 100 μm andnot more than 120 μm, not less than 120 μm and not more than 140 μm, notless than 140 μm and not more than 160 μm, not less than 160 μm and notmore than 180 μm, or not less than 180 μm and not more than 200 μm. Thethickness TL is preferably not less than 60 μm and not more than 150 μm.

In this embodiment, the first main surface 103 and the second mainsurface 104 face the c-planes of the SiC monocrystal. The first mainsurface 103 faces the (0001) plane (silicon plane). The second mainsurface 104 faces the (000-1) plane (carbon plane) of the SiCmonocrystal.

The first main surface 103 and the second main surface 104 have an offangle θ inclined at an angle of not more than 10° in the [11-20]direction with respect to the c-planes of the SiC monocrystal. Thenormal direction Z is inclined by just the off angle θ with respect tothe c-axis ([0001] direction) of the SiC monocrystal.

The off angle θ may be not less than 0° and not more than 5.0°. The offangle θ may be set in an angular range of not less than 0° and not morethan 1.0°, not less than 1.0° and not more than 1.5°, not less than 1.5°and not more than 2.0°, not less than 2.0° and not more than 2.5°, notless than 2.5° and not more than 3.0°, not less than 3.0° and not morethan 3.5°, not less than 3.5° and not more than 4.0°, not less than 4.0°and not more than 4.5°, or not less than 4.5° and not more than 5.0°.The off angle θ preferably exceeds 0°. The off angle θ may be less than4.0°.

The off angle θ may be set in an angular range of not less than 3.0° andnot more than 4.5°. In this case, the off angle θ is preferably set inan angular range of not less than 3.0° and not more than 3.5°, or notless than 3.5° and not more than 4.0°. The off angle θ may be set in anangular range of not less than 1.5° and not more than 3.0°. In thiscase, the off angle θ is preferably set in an angular range of not lessthan 1.5° and not more than 2.0°, or not less than 2.0° and not morethan 2.5°.

Lengths of the side surfaces 105A to 105D may each be not less than 1 mmand not more than 10 mm (for example, not less than 2 mm and not morethan 5 mm). In this embodiment, surface areas of the side surfaces 105Band 105D exceed surface areas of the side surfaces 105A and 105C. Thefirst main surface 103 and the second main surface 104 may be formed insquare shapes in plan view. In this case, the surface areas of the sidesurfaces 105A and 105C are equal to the surface areas of the sidesurfaces 105B and 105D.

In this embodiment, the side surface 105A and the side surface 105Cextend in a first direction X and oppose each other in a seconddirection Y intersecting the first direction X. In this embodiment, theside surface 105B and the side surface 105D extend in the seconddirection Y and oppose each other in the first direction X. Morespecifically, the second direction Y is orthogonal to the firstdirection X.

In this embodiment, the first direction X is set to the m-axis direction([1-100] direction) of the SiC monocrystal. The second direction Y isset to the a-axis direction ([11-20] direction) of the SiC monocrystal.

The side surface 105A and the side surface 105C form short sides of theSiC semiconductor layer 102 in plan view. The side surface 105A and theside surface 105C are formed by the a-planes of the SiC monocrystal andoppose each other in the a-axis direction. The side surface 105A isformed by the (−1-120) plane of the SiC monocrystal. The side surface105C is formed by the (11-20) plane of the SiC monocrystal.

The side surface 105A and the side surface 105C may form inclinedsurfaces that, when a normal to the first main surface 103 is taken as abasis, are inclined toward the c-axis direction ([0001] direction) ofthe SiC monocrystal with respect to the normal. In this case, the sidesurface 105A and the side surface 105C may be inclined at an angle inaccordance with the off angle θ with respect to the normal to the firstmain surface 103 when the normal to the first main surface 103 is 0°.The angle in accordance with the off angle θ may be equal to the offangle θ or may be an angle that exceeds 0° and is less than the offangle θ.

The side surface 105B and the side surface 105D form long sides of theSiC semiconductor layer 102 in plan view. The side surface 105B and theside surface 105D are formed by the m-planes of the SiC monocrystal andoppose each other in the m-axis direction. The side surface 105B isformed by the (−1100) plane of the SiC monocrystal. The side surface105D is formed by the (1-100) plane of the SiC monocrystal. The sidesurface 105B and the side surface 105D extend in plane shapes along thenormal to the first main surface 103. More specifically, the sidesurface 105B and the side surface 105D are formed substantiallyperpendicular to the first main surface 103 and the second main surface104.

In this embodiment, the SiC semiconductor layer 102 has a laminatedstructure that includes an n⁺ type SiC semiconductor substrate 106 andan n type SiC epitaxial layer 107. The SiC semiconductor substrate 106and the SiC epitaxial layer 107 respectively correspond to the SiCsemiconductor substrate 6 and the SiC epitaxial layer 7 according to thefirst preferred embodiment. The second main surface 104 of the SiCsemiconductor layer 102 is formed by the SiC semiconductor substrate106.

The first main surface 103 is formed by the SiC epitaxial layer 107. Theside surfaces 105A to 105D of the SiC semiconductor layer 102 are formedby the SiC semiconductor substrate 106 and the SiC epitaxial layer 107.

A thickness TS of the SiC semiconductor substrate 106 may be not lessthan 40 μm and not more than 150 μm. The thickness TS may be not lessthan 40 μm and not more than 50 μm, not less than 50 μm and not morethan 60 μm, not less than 60 μm and not more than 70 μm, not less than70 μm and not more than 80 μm, not less than 80 μm and not more than 90μm, not less than 90 μm and not more than 100 μm, not less than 100 μmand not more than 110 μm, not less than 110 μm and not more than 120 μm,not less than 120 μm and not more than 130 μm, not less than 130 μm andnot more than 140 μm, or not less than 140 μm and not more than 150 μm.The thickness TS is preferably not less than 40 μm and not more than 130μm. By thinning the SiC semiconductor substrate 106, a current path isshortened and reduction of resistance value can thus be achieved.

A thickness TE of the SiC epitaxial layer 107 may be not less than 1 μmand not more than 50 μm. The thickness TE may be not less than 1 μm andnot more than 5 μm, not less than 5 μm and not more than 10 μm, not lessthan 10 μm and not more than 15 μm, not less than 15 μm and not morethan 20 μm, not less than 20 μm and not more than 25 μm, not less than25 μm and not more than 30 μm, not less than 30 μm and not more than 35μm, not less than 35 μm and not more than 40 μm, not less than 40 μm andnot more than 45 μm, or not less than 45 μm and not more than 50 μm. Thethickness TE is preferably not less than 5 μm and not more than 15 μm.

An n type impurity concentration of the SiC epitaxial layer 107 is notmore than an n type impurity concentration of the SiC semiconductorsubstrate 106. More specifically, the n type impurity concentration ofthe SiC epitaxial layer 107 is less than the n type impurityconcentration of the SiC semiconductor substrate 106. The n typeimpurity concentration of the SiC semiconductor substrate 106 may be notless than 1.0×10¹⁵ cm⁻³ and not more than 1.0×10²¹ cm⁻³. The n typeimpurity concentration of the SiC epitaxial layer 107 may be not lessthan 1.0×10¹⁸ cm⁻³ and not more than 1.0×10¹⁸ cm⁻³.

In this embodiment, the SiC epitaxial layer 107 has a plurality ofregions having different n type impurity concentrations along the normaldirection Z. More specifically, the SiC epitaxial layer 107 includes ahigh concentration region 108 having a comparatively high n typeimpurity concentration and a low concentration region 109 having an ntype impurity concentration lower than the high concentration region108. The high concentration region 108 is formed in a region at thefirst main surface 103 side. The low concentration region 109 is formedin a region at the second main surface 104 side with respect to the highconcentration region 108.

The n type impurity concentration of the high concentration region 108may be not less than 1×10¹⁶ cm⁻³ and not more than 1×10¹⁸ cm⁻³. The ntype impurity concentration of the low concentration region 109 may benot less than 1×10¹⁵ cm⁻³ and not more than 1×10¹⁶ cm⁻³.

A thickness of the high concentration region 108 is not more than athickness of the low concentration region 109. More specifically, thethickness of the high concentration region 108 is less than thethickness of the low concentration region 109. The thickness of the highconcentration region 108 is less than one-half the total thickness ofthe SiC epitaxial layer 107.

The SiC semiconductor layer 102 includes an active region 111 and anouter region 112. The active region 111 is a region in which a verticalMISFET (metal insulator field effect transistor) is formed as an exampleof a functional device. In plan view, the active region 111 is formed ina central portion of the SiC semiconductor layer 102 at intervals towardan inner region from the side surfaces 105A to 105D. In plan view, theactive region 111 is formed in a quadrilateral shape (a rectangularshape in this embodiment) having four sides parallel to the four sidesurfaces 105A to 105D.

The outer region 112 is a region at an outer side of the active region111. The outer region 112 is formed in a region between the sidesurfaces 105A to 105D and peripheral edges of the active region 111. Theouter region 112 is formed in an endless shape (a quadrilateral annularshape in this embodiment) surrounding the active region 111 in planview.

The SiC semiconductor device 101 includes a main surface insulatinglayer 113 formed on the first main surface 103. The main surfaceinsulating layer 113 corresponds to the main surface insulating layer 10according to the first preferred embodiment. The main surface insulatinglayer 113 selectively covers the active region 111 and the outer region112. The main surface insulating layer 113 may include silicon oxide(SiO₂).

The main surface insulating layer 113 has four insulating side surfaces114A, 114B, 114C, and 114D exposed from the side surfaces 105A to 105D.The insulating side surfaces 114A to 114D are continuous to the sidesurfaces 105A to 105D. The insulating side surfaces 114A to 114D areformed flush with the side surfaces 105A to 105D. The insulating sidesurfaces 114A to 114D are constituted of cleavage surfaces.

A thickness of the main surface insulating layer 113 may be not lessthan 1 μm and not more than 50 μm. The thickness of the main surfaceinsulating layer 113 may be not less than 1 μm and not more than 10 μm,not less than 10 μm and not more than 20 μm, not less than 20 μm and notmore than 30 μm, not less than 30 μm and not more than 40 μm, or notless than 40 μm and not more than 50 μm.

The SiC semiconductor device 101 includes a main surface gate electrodelayer 115 formed on the main surface insulating layer 113 as one offirst main surface electrode layers. A gate voltage is applied to themain surface gate electrode layer 115. The gate voltage may be not lessthan 10 V and not more than 50 V (for example, approximately 30 V). Themain surface gate electrode layer 115 penetrates through the mainsurface insulating layer 113 and is electrically connected to anarbitrary region of the SiC semiconductor layer 102.

The main surface gate electrode layer 115 includes a gate pad 116 andgate fingers 117 and 118. The gate pad 116 and the gate fingers 117 and118 are arranged in the active region 111.

The gate pad 116 is formed along the side surface 105A in plan view. Thegate pad 116 is formed along a central region of the side surface 105Ain plan view. The gate pad 116 may be formed along a corner portionconnecting any two of the side surfaces 105A to 105D in plan view. Thegate pad 116 may be formed in a quadrilateral shape in plan view.

The gate fingers 117 and 118 include an outer gate finger 117 and aninner gate finger 118. The outer gate finger 117 is led out from thegate pad 116 and extends in a band shape along a peripheral edge of theactive region 111. In this embodiment, the outer gate finger 117 isformed along the three side surfaces 105A, 105B, and 105D such as todemarcate an inner region of the active region 111 from threedirections.

The outer gate finger 117 has a pair of open end portions 119 and 120.The pair of open end portions 119 and 120 are formed in a regionopposing the gate pad 116 across the inner region of the active region111. In this embodiment, the pair of open end portions 119 and 120 areformed along the side surface 105C.

The inner gate finger 118 is led out from the gate pad 116 to the innerregion of the active region 111. The inner gate finger 118 extends in aband shape in the inner region of the active region 111. The inner gatefinger 118 extends from the gate pad 116 toward the side surface 105C.

The SiC semiconductor device 101 includes a main surface sourceelectrode layer 121 formed on the main surface insulating layer 113 asone of the first main surface electrode layers. A source voltage isapplied to the main surface source electrode layer 121. The sourcevoltage may be a reference voltage (for example, a GND voltage). Themain surface source electrode layer 121 penetrates through the mainsurface insulating layer 113 and is electrically connected to anarbitrary region of the SiC semiconductor layer 102. In this embodiment,the main surface source electrode layer 121 includes a source pad 122, asource routing wiring 123, and a source connection portion 124.

The source pad 122 is formed in the active region 111 at intervals fromthe gate pad 116 and the gate fingers 117 and 118. The source pad 122 isformed in a C shape (an inverted C shape in FIG. 18 and FIG. 19) in planview such as to cover a region of C shape (inverted C shape in FIG. 18and FIG. 19) demarcated by the gate pad 116 and the gate fingers 117 and118.

The source routing wiring 123 is formed in the outer region 112. Thesource routing wiring 123 extends in a band shape along the activeregion 111. In this embodiment, the source routing wiring 123 is formedin an endless shape (a quadrilateral annular shape in this embodiment)surrounding the active region 111 in plan view. The source routingwiring 123 is electrically connected to the SiC semiconductor layer 102in the outer region 112.

The source connection portion 124 connects the source pad 122 and thesource routing wiring 123. The source connection portion 124 is formedin a region between the pair of open end portions 119 and 120 of theouter gate finger 117. The source connection portion 124 crosses aboundary region between the active region 111 and the outer region 112from the source pad 122 and is connected to the source routing wiring123.

The MISFET formed in the active region 111 includes an npn typeparasitic bipolar transistor due to its structure. When an avalanchecurrent generated in the outer region 112 flows into the active region111, the parasitic bipolar transistor is switched to an on state. Inthis case, control of the MISFET may become unstable, for example, dueto latchup.

Therefore, with the SiC semiconductor device 101, the structure of themain surface source electrode layer 121 is used to form an avalanchecurrent absorbing structure that absorbs the avalanche current generatedin the outer region 112. More specifically, the avalanche currentgenerated in the outer region 112 is absorbed by the source routingwiring 123 and reaches the source pad 122 via the source connectionportion 124. If a conductive wire (for example, a bonding wire) forexternal connection is connected to the source pad 122, the avalanchecurrent is taken out by this conductive wire.

Switching of the parasitic bipolar transistor to the on state by anundesirable current generated in the outer region 112 can thereby besuppressed. Latchup can thus be suppressed and therefore stability ofcontrol of the MISFET can be improved.

The SiC semiconductor device 101 includes a passivation layer 125(insulating layer) formed on the main surface insulating layer 113. Thepassivation layer 125 may have a single layer structure constituted of asilicon oxide layer or a silicon nitride layer. The passivation layer125 may have a laminated structure that includes a silicon oxide layerand a silicon nitride layer. The silicon oxide layer may be formed onthe silicon nitride layer. The silicon nitride layer may be formed onthe silicon oxide layer. In this embodiment, the passivation layer 125has a single layer structure constituted of a silicon nitride layer.

The passivation layer 125 includes four side surfaces 126A, 126B, 126C,and 126D. In plan view, the side surfaces 126A to 126D of thepassivation layer 125 are formed at intervals toward the inner regionfrom the side surfaces 105A to 105D of the SiC semiconductor layer 102.In plan view, the passivation layer 125 exposes a peripheral edgeportion of the SiC semiconductor layer 102. The passivation layer 125exposes the main surface insulating layer 113.

The passivation layer 125 selectively covers the main surface gateelectrode layer 115 and the main surface source electrode layer 121. Thepassivation layer 125 includes agate sub pad opening 127 and a sourcesub pad opening 128. The gate sub pad opening 127 exposes the gate pad116. The source sub pad opening 128 exposes the source pad 122.

A thickness of the passivation layer 125 may be not less than 1 μm andnot more than 50 μm. The thickness of the passivation layer 125 may benot less than 1 μm and not more than 10 μm, not less than 10 μm and notmore than 20 μm, not less than 20 μm and not more than 30 μm, not lessthan 30 μm and not more than 40 μm, or not less than 40 μm and not morethan 50 μm.

The SiC semiconductor device 101 includes a resin layer 129 (insulatinglayer) formed on the passivation layer 125. The passivation layer 125and the resin layer 129 form a single insulating laminated structure(insulating layer). In FIG. 18, the resin layer 129 is shown withhatching.

The resin layer 129 may include a negative type or positive typephotosensitive resin. In this embodiment, the resin layer 129 includes apolybenzoxazole as an example of a positive type photosensitive resin.The resin layer 129 may include a polyimide as an example of a negativetype photosensitive resin.

The resin layer 129 selectively covers the main surface gate electrodelayer 115 and the main surface source electrode layer 121. The resinlayer 129 includes four resin side surfaces 130A, 130B, 130C, and 130D.The resin side surfaces 130A to 130D are formed at intervals toward theinner region from the side surfaces 105A to 105D of the SiCsemiconductor layer 102. The resin layer 129, together with thepassivation layer 125, exposes the main surface insulating layer 113. Inthis embodiment, the resin side surfaces 130A to 130D are formed flushwith the side surfaces 126A to 126D of the passivation layer 125.

The resin side surfaces 130A to 130D of the resin layer 129, with theside surfaces 105A to 105D of the SiC semiconductor layer 102, demarcatea dicing street. In this embodiment, the side surfaces 126A to 126D ofthe passivation layer 125 also demarcate the dicing street. According tothe dicing street, it is made unnecessary to physically cut the resinlayer 129 and the passivation layer 125 when cutting out the SiCsemiconductor device 101 from a single SiC semiconductor wafer. The SiCsemiconductor device 101 can thereby be cut out smoothly from the singleSiC semiconductor wafer. Also, insulation distances from the sidesurfaces 105A to 105D can be increased.

A width of the dicing street may be not less than 1 μm and not more than25 μm. The width of the dicing street may be not less than 1 μm and notmore than 5 μm, not less than 5 μm and not more than 10 μm, not lessthan 10 μm and not more than 15 μm, not less than 15 μm and not morethan 20 μm, or not less than 20 μm and not more than 25 μm.

The resin layer 129 includes a gate pad opening 131 and a source padopening 132. The gate pad opening 131 exposes the gate pad 116. Thesource pad opening 132 exposes the source pad 122.

The gate pad opening 131 is in communication with the gate sub padopening 127 of the passivation layer 125. Inner walls of the gate padopening 131 may be positioned at outer sides of inner walls of the gatesub pad opening 127. The inner walls of the gate pad opening 131 may bepositioned at inner sides of the inner walls of the gate sub pad opening127. The resin layer 129 may cover the inner walls of the gate sub padopening 127.

The source pad opening 132 is in communication with the source sub padopening 128 of the passivation layer 125. The inner walls of the gatepad opening 131 may be positioned at outer sides of inner walls of thesource sub pad opening 128. Inner walls of the source pad opening 132may be positioned at inner sides of the inner walls of the source subpad opening 128. The resin layer 129 may cover the inner walls of thesource sub pad opening 128.

A thickness of the resin layer 129 may be not less than 1 μm and notmore than 50 μm. The thickness of the resin layer 129 may be not lessthan 1 μm and not more than 10 μm, not less than 10 μm and not more than20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μmand not more than 40 μm, or not less than 40 μm and not more than 50 μm.

The SiC semiconductor device 101 includes a drain electrode layer 133formed on the second main surface 104 as a second main surface electrodelayer. The drain electrode layer 133 forms an ohmic contact with thesecond main surface 104 (SiC semiconductor substrate 106). That is, theSiC semiconductor substrate 106 is formed as a drain region 134 of theMISFET. Also, the SiC epitaxial layer 107 is formed as a drift region135 of the MISFET. A maximum voltage applicable between the main surfacesource electrode layer 121 and the drain electrode layer 133 in an offstate may be not less than 1000 V and not more than 10000 V.

The drain electrode layer 133 may include at least one layer among a Tilayer, an Ni layer, an Au layer, an Ag layer, and an Al layer. The drainelectrode layer 133 may have a single layer structure that includes a Tilayer, an Ni layer, an Au layer, an Ag layer, or an Al layer. The drainelectrode layer 133 may have a laminated structure in which at least twolayers among a Ti layer, an Ni layer, an Au layer, an Ag layer, and anAl layer are laminated in any mode. The drain electrode layer 133 mayhave a four-layer structure that includes a Ti layer, an Ni layer, an Aulayer, and an Ag layer that are laminated in that order from the secondmain surface 104.

The SiC semiconductor device 101 includes the plurality of modifiedlines 22A to 22D according to the first configuration example that areformed at the side surfaces 105A to 105D of the SiC semiconductor layer102. The structure of the modified lines 22A to 22D of the SiCsemiconductor device 101 is the same as the structure of the modifiedlines 22A to 22D of the SiC semiconductor device 1 with the exception ofthe point of being formed in the SiC semiconductor layer 102 instead ofthe SiC semiconductor layer 2.

The descriptions of the modified lines 22A to 22D of the SiCsemiconductor device 1 apply respectively to the modified lines 22A to22D of the SiC semiconductor device 101. Specific descriptions of themodified lines 22A to 22D of the SiC semiconductor device 101 shall beomitted.

The SiC semiconductor device 101 includes the plurality of boundarymodified lines 30A to 30D formed at the side surfaces 105A to 105D ofthe SiC semiconductor layer 102 and the insulating side surfaces 114A to114D of the main surface insulating layer 113. The structure of theboundary modified lines 30A to 30D of the SiC semiconductor device 101is the same as the structure of the boundary modified lines 30A to 30Dof the SiC semiconductor device 1 with the exception of the point ofbeing formed in a boundary region between the SiC semiconductor layer102 and the main surface insulating layer 113 instead of the boundaryregion between the SiC semiconductor layer 2 and the main surfaceinsulating layer 10.

The descriptions of the boundary modified lines 30A to 30D of the SiCsemiconductor device 1 apply respectively to the boundary modified lines30A to 30D of the SiC semiconductor device 101. Specific descriptions ofthe boundary modified lines 30A to 30D of the SiC semiconductor device101 shall be omitted.

FIG. 20 is an enlarged view of a region XX shown in FIG. 19 and is adiagram for describing the structure of the first main surface 103. FIG.21 is a sectional view taken along line XXI-XXI shown in FIG. 20. FIG.22 is a sectional view taken along line XXII-XXII shown in FIG. 20. FIG.23 is an enlarged view of a region XXIII shown in FIG. 21. FIG. 24 is asectional view taken along line XXIV-XXIV shown in FIG. 19. FIG. 25 isan enlarged view of a region XXV shown in FIG. 24.

Referring to FIG. 20 to FIG. 24, the SiC semiconductor device 101includes a p type body region 141 formed in a surface layer portion ofthe first main surface 103 in the active region 111. In this embodiment,the body region 141 is formed over an entire area of a region of thefirst main surface 103 forming the active region 111. The body region141 thereby defines the active region 111. A p type impurityconcentration of the body region 141 may be not less than 1.0×10¹⁷ cm⁻³and not more than 1.0×10¹⁹ cm⁻³.

The SiC semiconductor device 101 includes a plurality of gate trenches142 formed in the surface layer portion of the first main surface 103 inthe active region 111. In plan view, the plurality of gate trenches 142are respectively formed in band shapes extending along the firstdirection X (the m-axis direction of the SiC monocrystal) and are formedat intervals along the second direction Y (the a-axis direction of theSiC monocrystal).

In this embodiment, each gate trench 142 extends from a peripheral edgeportion at one side (the side surface 105B side) toward a peripheraledge portion at another side (the side surface 105D side) of the activeregion 111. The plurality of gate trenches 142 are formed in a stripeshape as a whole in plan view.

Each gate trench 142 crosses an intermediate portion between theperipheral edge portion at the one side and the peripheral edge portionat the other side of the active region 111. One end portion of each gatetrench 142 is positioned at the peripheral edge portion at the one sideof the active region 111. Another end portion of each gate trench 142 ispositioned at the peripheral edge portion at the other side of theactive region 111.

A length of each gate trench 142 may be not less than 0.5 mm. The lengthof each gate trench 142 is, in the section shown in FIG. 22, a lengthfrom the end portion at the side of a connection portion of each gatetrench 142 and the outer gate finger 117 to the end portion at theopposite side. In this embodiment, the length of each gate trench 142 isnot less than 1 mm and not more than 10 mm (for example, not less than 2mm and not more than 5 mm). A total extension of one or a plurality ofthe gate trenches 142 per unit area may be not less than 0.5 μm/μm² andnot more than 0.75 μm/μm².

Each gate trench 142 integrally includes an active trench portion 143and a contact trench portion 144. The active trench portion 143 is aportion in the active region 111 oriented along a channel of the MISFET.

The contact trench portion 144 is a portion of the gate trench 142 thatmainly serves as a contact with the outer gate finger 117. The contacttrench portion 144 is led out from the active trench portion 143 to theperipheral edge portion of the active region 111. The contact trenchportion 144 is formed in a region directly below the outer gate finger117. A lead-out amount of the contact trench portion 144 is arbitrary.

Each gate trench 142 penetrates through the body region 141 and reachesthe SiC epitaxial layer 107. Each gate trench 142 includes side wallsand a bottom wall. The side walls that form long sides of each gatetrench 142 are formed by the a-planes of the SiC monocrystal. The sidewalls that form short sides of each gate trench 142 are formed by them-planes of the SiC monocrystal.

The side walls of each gate trench 142 may extend along the normaldirection Z. The side walls of each gate trench 142 may be formedsubstantially perpendicular to the first main surface 103. Angles thatthe side walls of each gate trench 142 form with respect to the firstmain surface 103 inside the SiC semiconductor layer 102 may be not lessthan 90° and not more than 95° (for example, not less than 91° and notmore than 93°). Each gate trench 142 may be formed in a tapered shapewith an opening area at the bottom wall side being smaller than anopening area at an opening side in sectional view.

The bottom wall of each gate trench 142 is positioned at the SiCepitaxial layer 107. More specifically, the bottom wall of each gatetrench 142 is positioned at the high concentration region 108 of the SiCepitaxial layer 107. The bottom wall of each gate trench 142 faces thec-plane of the SiC monocrystal. The bottom wall of each gate trench 142has the off angle θ inclined in the [11-20] direction with respect tothe c-plane of the SiC monocrystal.

The bottom wall of each gate trench 142 may be formed parallel to thefirst main surface 103. Obviously, the bottom wall of each gate trench142 may be formed in a curved shape toward the second main surface 104.

A depth in the normal direction Z of each gate trench 142 may be notless than 0.5 μm and not more than 3.0 μm. The depth of each gate trench142 may be not less than 0.5 μm and not more than 1.0 μm, not less than1.0 μm and not more than 1.5 μm, not less than 1.5 μm and not more than2.0 μm, not less than 2.0 μm and not more than 2.5 μm, or not less than2.5 μm and not more than 3.0 μm.

A width of each gate trench 142 along the second direction Y may be notless than 0.1 μm and not more than 2 μm. The width of each gate trench142 may be not less than 0.1 μm and not more than 0.5 μm, not less than0.5 μm and not more than 1.0 μm, not less than 1.0 μm and not more than1.5 μm, or not less than 1.5 μm and not more than 2 μm.

Referring to FIG. 23, an opening edge portion 146 of each gate trench142 includes an inclined portion 147 that is inclined downwardly fromthe first main surface 103 toward an inner side of each gate trench 142.The opening edge portion 146 of each gate trench 142 is a corner portionconnecting the first main surface 103 and the side walls of each gatetrench 142.

In this embodiment, the inclined portion 147 is formed in a curved shaperecessed toward the SiC semiconductor layer 102 side. The inclinedportion 147 may be formed in a curved shape protruding toward thecorresponding gate trench 142 side. The inclined portion 147 relaxesconcentration of electric field with respect to the opening edge portion146 of the corresponding gate trench 142.

The SiC semiconductor device 101 includes a gate insulating layer 148and a gate electrode layer 149 that are formed inside the respectivegate trenches 142. In FIG. 20, the gate insulating layers 148 and thegate electrode layers 149 are shown with hatching.

The gate insulating layer 148 includes at least one type of materialamong silicon oxide (SiO₂), silicon nitride (SiN), aluminum oxide(Al₂O₃), zirconium oxide (ZrO₂), and tantalum oxide (Ta₂O₃). The gateinsulating layer 148 may have a laminated structure that includes an SiNlayer and an SiO₂ layer that are laminated in that order from the SiCsemiconductor layer 102 side.

The gate insulating layer 148 may have a laminated structure thatincludes an SiO₂ layer and an SiN layer that are laminated in that orderfrom the SiC semiconductor layer 102 side. The gate insulating layer 148may have a single layer structure constituted of an SiO₂ layer or an SiNlayer. In this embodiment, the gate insulating layer 148 has a singlelayer structure constituted of an SiO₂ layer.

The gate insulating layer 148 is formed in a film along inner wallsurfaces of each gate trench 142 and demarcates a recess space insidethe gate trench 142. The gate insulating layer 148 includes firstregions 148 a, second regions 148 b, and third regions 148 c.

Each first region 148 a is formed along the side walls of thecorresponding gate trench 142. Each second region 148 b is formed alongthe bottom wall of the corresponding gate trench 142. Each third region148 c is formed along the first main surface 103. The third region 148 cof the gate insulating layer 148 forms a portion of the main surfaceinsulating layer 113.

A thickness Ta of the first region 148 a is less than a thickness Tb ofthe second region 148 b and a thickness Tc of the third region 148 c. Aratio Tb/Ta of the thickness Tb of the second region 148 b with respectto the thickness Ta of the first region 148 a may be not less than 2 andnot more than 5. A ratio T3/Ta of the thickness Tc of the third region148 c with respect to the thickness Ta of the first region 148 a may benot less than 2 and not more than 5.

The thickness Ta of the first region 148 a may be not less than 0.01 μmand not more than 0.2 μm. The thickness Tb of the second region 148 bmay be not less than 0.05 μm and not more than 0.5 μm. The thickness Tcof the third region 148 c may be not less than 0.05 μm and not more than0.5 μm.

By making the first region 148 a thin, increase in carriers induced inregions of the body region 141 in vicinities of the side walls of thecorresponding gate trench 142 can be suppressed. Increase in channelresistance can thereby be suppressed. By making the second region 148 bthick, concentration of electric field with respect to the bottom wallof the corresponding gate trench 142 can be relaxed.

By making the third region 148 c thick, a withstand voltage of the gateinsulating layer 148 in a vicinity of the opening edge portion 146 ofeach gate trench 142 can be improved. Also, by making the third region148 c thick, loss of the third region 148 c due to an etching method canbe suppressed.

The first region 148 a can thereby be suppressed from being removed bythe etching method due to the loss of the third region 148 c.Consequently, each gate electrode layer 149 can be made to oppose theSiC semiconductor layer 102 (body region 141) appropriately across thecorresponding gate insulating layer 148.

The gate insulating layer 148 further includes a bulging portion 148 dbulging toward an interior of the corresponding gate trench 142 at theopening edge portion 146 of the corresponding gate trench 142. Thebulging portion 148 d is formed at a corner portion connecting thecorresponding first region 148 a and third region 148 c of the gateinsulating layer 148.

The bulging portion 148 d bulges curvingly toward the interior of thecorresponding gate trench 142. The bulging portion 148 d narrows anopening of the corresponding gate trench 142 at the opening edge portion146 of the corresponding gate trench 142.

The bulging portion 148 d improves a dielectric withstand voltage of thegate insulating layer 148 at the opening edge portions 146. Obviously,the gate insulating layer 148 not having the bulging portions 148 d maybe formed. Also, the gate insulating layer 148 having a uniformthickness may be formed.

Each gate electrode layer 149 is embedded in the corresponding gatetrench 142 across the gate insulating layer 148. More specifically, thegate electrode layer 149 is embedded in the recess space demarcated bythe gate insulating layer 148 in the corresponding gate trench 142. Thegate electrode layer 149 is controlled by the gate voltage.

The gate electrode layer 149 has an upper end portion positioned at theopening side of the corresponding gate trench 142. The upper end portionof the gate electrode layer 149 is formed in a curved shape recessedtoward the bottom wall of the corresponding gate trench 142. The upperend portion of the gate electrode layer 149 has a constricted portionthat is constricted along the bulging portion 148 d of the gateinsulating layer 148.

A cross-sectional area of the gate electrode layer 149 may be not lessthan 0.05 μm² and not more than 0.5 μm². The cross-sectional area of thegate electrode layer 149 is an area of a section that appears when thegate electrode layer 149 is cut in a direction orthogonal to thedirection in which the gate trench 142 extends. The cross-sectional areaof the gate electrode layer 149 is defined as a product of a depth ofthe gate electrode layer 149 and a width of the gate electrode layer149.

The depth of the gate electrode layer 149 is a distance from the upperend portion to a lower end portion of the gate electrode layer 149. Thewidth of the gate electrode layer 149 is a width of the gate trench 142at an intermediate position between the upper end portion and the lowerend portion of the gate electrode layer 149. If the upper end portion isa curved surface, the position of the upper end portion of the gateelectrode layer 149 is deemed to be an intermediate position of theupper end portion of the gate electrode layer 149.

The gate electrode layer 149 includes a p type polysilicon doped with ap type impurity. The p type impurity of the gate electrode layer 149 mayinclude at least one type of material among boron (B), aluminum (Al),indium (In), and gallium (Ga).

A p type impurity concentration of the gate electrode layer 149 is notless than the p type impurity concentration of the body region 141. Morespecifically, the p type impurity concentration of the gate electrodelayer 149 exceeds the p type impurity concentration of the body region141. The p type impurity concentration of the gate electrode layer 149may be not less than 1×10¹⁸ cm⁻³ and not more than 1×10²² cm⁻³. A sheetresistance of the gate electrode layer 149 may be not less than 10Ω/□and not more than 500Ω/□ (approximately 200Ω/□ in this embodiment).

Referring to FIG. 20 and FIG. 22, the SiC semiconductor device 101includes a gate wiring layer 150 formed in the active region 111. Thegate wiring layer 150 is electrically connected to the gate pad 116 andthe gate fingers 117 and 118. In FIG. 22, the gate wiring layer 150 isshown with hatching.

The gate wiring layer 150 is formed on the first main surface 103. Morespecifically, the gate wiring layer 150 is formed on the third regions148 c of the gate insulating layer 148. In this embodiment, the gatewiring layer 150 is formed along the outer gate finger 117. Morespecifically, the gate wiring layer 150 is formed along the three sidesurfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 such asto demarcate the inner region of the active region 111 from threedirections.

The gate wiring layer 150 is connected to the gate electrode layer 149exposed from the contact trench portion 144 of each gate trench 142. Inthis embodiment, the gate wiring layer 150 is formed by lead-outportions of the gate electrode layers 149 that are led out from therespective gate trenches 142 onto the first main surface 103. An upperend portion of the gate wiring layer 150 is connected to the upper endportions of the gate electrode layers 149.

Referring to FIG. 20, FIG. 21 and FIG. 23, the SiC semiconductor device101 includes a plurality of source trenches 155 formed in the first mainsurface 103 in the active region 111. Each source trench 155 is formedin a region between two mutually adjacent gate trenches 142.

The plurality of source trenches 155 are each formed in a band shapeextending along the first direction X (the m-axis direction of the SiCmonocrystal). The plurality of source trenches 155 are formed in astripe shape as a whole in plan view. A pitch in the second direction Ybetween central portions of source trenches 155 that are mutuallyadjacent may be not less than 1.5 μm and not more than 3 μm.

Each source trench 155 penetrates through the body region 141 andreaches the SiC epitaxial layer 107. Each source trench 155 includesside walls and a bottom wall. The side walls that form long sides ofeach source trench 155 are formed by the a-planes of the SiCmonocrystal. The side walls that form short sides of each source trench155 are formed by the m-planes of the SiC monocrystal.

The side walls of each source trench 155 may extend along the normaldirection Z. The side walls of each source trench 155 may be formedsubstantially perpendicular to the first main surface 103. Angles thatthe side walls of each source trench 155 form with respect to the firstmain surface 103 inside the SiC semiconductor layer 102 may be not lessthan 90° and not more than 95° (for example, not less than 91° and notmore than 93°). Each source trench 155 may be formed in a tapered shapewith an opening area at the bottom wall side being smaller than anopening area at an opening side in sectional view.

The bottom wall of each source trench 155 is positioned inside the SiCepitaxial layer 107. More specifically, the bottom wall of each sourcetrench 155 is positioned at the high concentration region 108 of the SiCepitaxial layer 107. The bottom wall of each source trench 155 ispositioned at the second main surface 104 side with respect to thebottom wall of each gate trench 142. The bottom wall of each sourcetrench 155 is positioned at a region between the bottom wall of eachgate trench 142 and the low concentration region 109.

The bottom wall of each source trench 155 faces the c-plane of the SiCmonocrystal. The bottom wall of each source trench 155 has the off angleθ inclined in the [11-20] direction with respect to the c-plane of theSiC monocrystal. The bottom wall of each source trench 155 may be formedparallel to the first main surface 103. The bottom wall of each sourcetrench 155 may be formed in a curved shape toward the second mainsurface 104.

In this embodiment, a depth of each source trench 155 is not less thanthe depth of each gate trench 142. More specifically, the depth of eachsource trench 155 is greater than the depth of each gate trench 142. Thedepth of each source trench 155 may be equal to the depth of each gatetrench 142.

The depth in the normal direction Z of each source trench 155 may be notless than 0.5 μm and not more than 10 μm (for example, approximately 2μm). A ratio of the depth of each source trench 155 with respect to thedepth of each gate trench 142 may be not less than 1.5. The ratio of thedepth of each source trench 155 with respect to the depth of each gatetrench 142 is preferably not less than 2.

A first direction width of each source trench 155 may be substantiallyequal to the first direction width of each gate trench 142. The firstdirection width of each source trench 155 may be not less than the firstdirection width of each gate trench 142. The first direction width ofeach source trench 155 may be not less than 0.1 μm and not more than 2μm (for example, approximately 0.5 μm).

The SiC semiconductor device 101 includes a source insulating layer 156and a source electrode layer 157 that are formed inside each sourcetrench 155. In FIG. 20, the source insulating layers 156 and the sourceelectrode layers 157 are shown with hatching.

Each source insulating layer 156 includes at least one type of materialamong silicon oxide (SiO₂), silicon nitride (SiN), aluminum oxide(Al₂O₃), zirconium oxide (ZrO₂), and tantalum oxide (Ta₂O₃). The sourceinsulating layer 156 may have a laminated structure that includes an SiNlayer and an SiO₂ layer that are laminated in that order from the firstmain surface 103 side.

The source insulating layer 156 may have a laminated structure thatincludes an SiO₂ layer and an SiN layer that are laminated in that orderfrom the first main surface 103 side. The source insulating layer 156may have a single layer structure constituted of an SiO₂ layer or an SiNlayer. In this embodiment, the source insulating layer 156 has a singlelayer structure constituted of an SiO₂ layer.

The source insulating layer 156 is formed in a film along inner wallsurfaces of the corresponding source trench 155 and demarcates a recessspace inside the corresponding source trench 155. The source insulatinglayer 156 includes a first region 156 a and a second region 156 b.

The first region 156 a is formed along the side walls of thecorresponding source trench 155. The second region 156 b is formed alongthe bottom wall of the corresponding source trench 155. A thickness Tsaof the first region 156 a is less than a thickness Tsb of the secondregion 156 b.

A ratio Tsb/Tsa of the thickness Tsb of the second region 156 b withrespect to the thickness Tsa of the first region 156 a may be not lessthan 2 and not more than 5. The thickness Tsa of the first region 156 amay be not less than 0.01 μm and not more than 0.2 μm. The thickness Tsbof the second region 156 b may be not less than 0.05 μm and not morethan 0.5 μm.

The thickness Tsa of the first region 156 a may be substantially equalto the thickness Ta of the first region 156 a of the gate insulatinglayer 148. The thickness Tsb of the second region 156 b may besubstantially equal to the thickness Tb of the second region 156 b ofthe gate insulating layer 148. Obviously, a source insulating layer 156having a uniform thickness may be formed.

Each source electrode layer 157 is embedded in the corresponding sourcetrench 155 across the source insulating layer 156. More specifically,the source electrode layer 157 is embedded in the recess spacedemarcated by the source insulating layer 156 in the correspondingsource trench 155. The source electrode layer 157 is controlled by thesource voltage.

The source electrode layer 157 has an upper end portion positioned at anopening side of the corresponding source trench 155. The upper endportion of the source electrode layer 157 is formed at the bottom wallside of the source trench 155 with respect to the first main surface103. The upper end portion of the source electrode layer 157 may bepositioned higher than the first main surface 103.

The upper end portion of the source electrode layer 157 is formed in aconcavely curved shape recessed toward the bottom wall of thecorresponding source trench 155. The upper end portion of the sourceelectrode layer 157 may be formed parallel to the first main surface103.

The upper end portion of the source electrode layer 157 may protrudehigher than an upper end portion of the source insulating layer 156. Theupper end portion of the source electrode layer 157 may be positioned atthe bottom wall side of the source trench 155 with respect to the upperend portion of the source insulating layer 156. A thickness of thesource electrode layer 157 may be not less than 0.5 μm and not more than10 μm (for example, approximately 1 μm).

The source electrode layer 157 preferably includes a polysilicon havingproperties close to SiC in terms of material properties. Stressgenerated in the SiC semiconductor layer 102 can thereby be reduced. Inthis embodiment, the source electrode layer 157 includes a p typepolysilicon doped with a p type impurity. In this case, the sourceelectrode layer 157 can be formed at the same time as the gate electrodelayer 149. The p type impurity of the source electrode layer 157 mayinclude at least one type of material among boron (B), aluminum (Al),indium (In), and gallium (Ga).

A p type impurity concentration of the source electrode layer 157 is notless than the p type impurity concentration of the body region 141. Morespecifically, the p type impurity concentration of the source electrodelayer 157 exceeds the p type impurity concentration of the body region141. The p type impurity concentration of the source electrode layer 157may be not less than 1×10¹⁸ cm⁻³ and not more than 1×10²² cm-³.

A sheet resistance of the source electrode layer 157 may be not lessthan 10Ω/□ and not more than 500Ω/□ (approximately 200Ω/□ in thisembodiment). The p type impurity concentration of the source electrodelayer 157 may be substantially equal to the p type impurityconcentration of the gate electrode layer 149. The sheet resistance ofthe source electrode layer 157 may be substantially equal to the sheetresistance of the gate electrode layer 149.

The source electrode layer 157 may include an n type polysilicon inplace of or in addition to the p type polysilicon. The source electrodelayer 157 may include at least one type of material among tungsten,aluminum, copper, an aluminum alloy, and a copper alloy in place of orin addition to the p type polysilicon.

The SiC semiconductor device 101 thus has a plurality of trench gatestructures 161 and a plurality of trench source structures 162. Eachtrench gate structure 161 includes the gate trench 142, the gateinsulating layer 148, and the gate electrode layer 149. Each trenchsource structure 162 includes the source trench 155, the sourceinsulating layer 156, and the source electrode layer 157.

The SiC semiconductor device 101 includes n⁺ type source regions 163formed in regions of a surface layer portion of the body region 141along the side walls of each gate trench 142. An n type impurityconcentration of the source regions 163 may be not less than 1.0×10¹⁸cm⁻³ and not more than 1.0×10²¹ cm⁻³. An n type impurity of the sourceregions 163 may be phosphorus (P).

A plurality of the source regions 163 are formed along the side wall atone side and the side wall at another side of each gate trench 142. Theplurality of source regions 163 are respectively formed in band shapesextending along the first direction X. The plurality of source regions163 are formed in a stripe shape as a whole in plan view. The respectivesource regions 163 are exposed from the side walls of the respectivegate trenches 142 and the side walls of the respective source trenches155.

The source regions 163, the body region 141, and the drift region 135are thus formed in that order from the first main surface 103 toward thesecond main surface 104 in regions of the surface layer portion of thefirst main surface 103 along the side walls of the gate trenches 142.The channels of the MISFET are formed in regions of the body region 141along the side walls of the gate trenches 142. The channels are formedin the regions along the side walls of the gate trenches 142 facing thea-planes of the SiC monocrystal. ON/OFF of the channels is controlled bythe gate electrode layers 149.

The SiC semiconductor device 101 includes a plurality of p⁺ type contactregions 164 formed in the surface layer portion of the first mainsurface 103 in the active region 111. Each contact region 164 is formedin a region between two mutually adjacent gate trenches 142 in planview. Each contact region 164 is formed in a region opposite thecorresponding gate trench 142 with respect to the corresponding sourceregion 163.

Each contact region 164 is formed along an inner wall of thecorresponding source trench 155. In this embodiment, a plurality ofcontact regions 164 are formed at intervals along the inner walls ofeach source trench 155. Each contact region 164 is formed at intervalsfrom the corresponding gate trenches 142.

A p type impurity concentration of each contact region 164 is greaterthan the p type impurity concentration of the body region 141. The ptype impurity concentration of each contact region 164 may be not lessthan 1.0×10¹⁸ cm⁻³ and not more than 1.0×10²¹ cm⁻³. A p type impurity ofeach contact region 164 may be aluminum (Al).

Each contact region 164 covers the side walls and the bottom wall of thecorresponding source trench 155. A bottom portion of each contact region164 may be formed parallel to the bottom wall of the correspondingsource trench 155. More specifically, each contact region 164 integrallyincludes a first surface layer region 164 a, a second surface layerregion 164 b, and an inner wall region 164 c.

The first surface layer region 164 a covers the side wall at one side ofthe source trench 155 in the surface layer portion of the body region141. The first surface layer region 164 a is electrically connected tothe body region 141 and the source region 163.

The first surface layer region 164 a is positioned at a region at thefirst main surface 103 side with respect to a bottom portion of thesource region 163. In this embodiment, the first surface layer region164 a has a bottom portion extending in parallel to the first mainsurface 103. In this embodiment, the bottom portion of the first surfacelayer region 164 a is positioned at a region between a bottom portion ofthe body region 141 and the bottom portion of the source region 163. Thebottom portion of the first surface layer region 164 a may be positionedat a region between the first main surface 103 and the bottom portion ofthe body region 141.

In this embodiment, the first surface layer region 164 a is led out fromthe source trench 155 toward the gate trench 142 adjacent thereto. Thefirst surface layer region 164 a may extend to an intermediate regionbetween the gate trench 142 and the source trench 155. The first surfacelayer region 164 a is formed at an interval toward the source trench 155side from the gate trench 142.

The second surface layer region 164 b covers the side wall at the otherside of the source trench 155 in the surface layer portion of the bodyregion 141. The second surface layer region 164 b is electricallyconnected to the body region 141 and the source region 163. The secondsurface layer region 164 b is positioned at a region at the first mainsurface 103 side with respect to the bottom portion of the source region163. In this embodiment, the second surface layer region 164 b has abottom portion extending in parallel to the first main surface 103.

In this embodiment, the bottom portion of the second surface layerregion 164 b is positioned at a region between the bottom portion of thebody region 141 and the bottom portion of the source region 163. Thebottom portion of the second surface layer region 164 b may bepositioned at a region between the first main surface 103 and the bottomportion of the body region 141.

In this embodiment, the second surface layer region 164 b is led outfrom the side wall at the other side of the source trench 155 toward thegate trench 142 adjacent thereto. The second surface layer region 164 bmay extend to an intermediate region between the source trench 155 andthe gate trench 142. The second surface layer region 164 b is formed atan interval toward the source trench 155 side from the gate trench 142.

The inner wall region 164 c is positioned at a region at the second mainsurface 104 side with respect to the first surface layer region 164 aand the second surface layer region 164 b (the bottom portion of thesource region 163). The inner wall region 164 c is formed in a region ofthe SiC semiconductor layer 102 along the inner walls of the sourcetrench 155. The inner wall region 164 c covers the side walls of thesource trench 155.

The inner wall region 164 c covers a corner portion connecting the sidewalls and the bottom wall of the source trench 155. The inner wallregion 164 c covers the bottom wall of the source trench 155 from theside walls and via the corner portion of the source trench 155. Thebottom portion of the contact region 164 is formed by the inner wallregion 164 c.

The SiC semiconductor device 101 includes a plurality of deep wellregions 165 formed in the surface layer portion of the first mainsurface 103 in the active region 111. Each deep well region 165 is alsoreferred to as a withstand voltage adjustment region (withstand voltageholding region) that adjusts the withstand voltage of the SiCsemiconductor layer 102.

Each deep well region 165 is formed in the SiC epitaxial layer 107. Morespecifically, each deep well region 165 is formed in the highconcentration region 108 of the SiC epitaxial layer 107.

Each deep well region 165 is formed along the inner walls of thecorresponding source trench 155 such as to cover the correspondingcontact regions 164. Each deep well region 165 is electrically connectedto the corresponding contact regions 164. Each deep well region 165 isformed in a band shape extending along the corresponding source trench155 in plan view. Each deep well region 165 covers the side walls of thecorresponding source trench 155.

Each deep well region 165 covers the corner portion connecting the sidewalls and the bottom wall of the corresponding source trench 155. Eachdeep well region 165 covers the bottom wall of the corresponding sourcetrench 155 from the side walls and via the corner portion of thecorresponding source trench 155. Each deep well region 165 is continuousto the body region 141 at the side walls of the corresponding sourcetrench 155.

Each deep well region 165 has a bottom portion positioned at the secondmain surface 104 side with respect to the bottom wall of thecorresponding gate trench 142. The bottom portion of each deep wellregion 165 may be formed parallel to the bottom wall of thecorresponding source trench 155.

A p type impurity concentration of each deep well region 165 may besubstantially equal to the p type impurity concentration of the bodyregion 141. The p type impurity concentration of each deep well region165 may exceed the p type impurity concentration of the body region 141.The p type impurity concentration of each deep well region 165 may beless than the p type impurity concentration of the body region 141.

The p type impurity concentration of each deep well region 165 may benot more than the p type impurity concentration of the contact regions164. The p type impurity concentration of each deep well region 165 maybe less than the p type impurity concentration of the contact regions164. The p type impurity concentration of each deep well region 165 maybe not less than 1.0×10¹⁷ cm⁻³ and not more than 1.0×10¹⁹ cm⁻³.

Each deep well region 165 forms a pn junction portion with the SiCsemiconductor layer 102 (the high concentration region 108 of the SiCepitaxial layer 107). From the pn junction portion, a depletion layerspreads toward a region between the plurality of gate trenches 142 thatare mutually adjacent. The depletion layer spreads toward a region atthe second main surface 104 side with respect to the bottom wall of eachgate trench 142.

The depletion layer spreading from each deep well region 165 may overlapwith the bottom walls of the corresponding gate trenches 142. Thedepletion layer spreading from the bottom portion of each deep wellregion 165 may overlap with the bottom walls of the corresponding gatetrenches 142.

Referring to FIG. 20 and FIG. 22, the SiC semiconductor device 101includes a p type peripheral edge deep well region 166 formed in aperipheral edge portion of the active region 111. The peripheral edgedeep well region 166 is formed in the SiC epitaxial layer 107. Morespecifically, the peripheral edge deep well region 166 is formed in thehigh concentration region 108 of the SiC epitaxial layer 107.

The peripheral edge deep well region 166 is electrically connected tothe respective deep well regions 165. The peripheral edge deep wellregion 166 forms an equal potential with the respective deep wellregions 165. In this embodiment, the peripheral edge deep well region166 is formed integral to the respective deep well regions 165.

More specifically, in the peripheral edge portion of the active region111, the peripheral edge deep well region 166 is formed in regions alongthe inner wall of the contact trench portions 144 of the respective gatetrenches 142. The peripheral edge deep well region 166 covers the sidewalls of the contact trench portions 144 of the respective gate trenches142. The peripheral edge deep well region 166 covers corner portionsconnecting the side walls and the bottom walls of the respective contacttrench portions 144.

The peripheral edge deep well region 166 covers the bottom walls of therespective contact trench portions 144 from the side walls and via thecorner portions of the respective contact trench portions 144. Therespective deep well regions 165 are continuous to the body region 141at the side walls of the corresponding contact trench portions 144. Abottom portion of the peripheral edge deep well region 166 is positionedat the second main surface 104 side with respect to the bottom walls ofthe respective contact trench portions 144.

The peripheral edge deep well region 166 overlaps with the gate wiringlayer 150 in plan view. The peripheral edge deep well region 166 opposesthe gate wiring layer 150 across the gate insulating layer 148 (thethird regions 148 c).

The peripheral edge deep well region 166 includes lead-out portions 166a led out to the respective active trench portions 143 from thecorresponding contact trench portions 144. The lead-out portions 166 aare formed in the high concentration region 108 of the SiC epitaxiallayer 107. Each lead-out portion 166 a extends along the side walls ofthe corresponding active trench portion 143 and covers the bottom wallof the active trench portion 143 through a corner portion.

The lead-out portion 166 a covers the side walls of the correspondingactive trench portion 143. The lead-out portion 166 a covers the cornerportion connecting the side walls and the bottom wall of thecorresponding active trench portion 143. The lead-out portion 166 acovers the bottom wall of the corresponding active trench portion 143from the side walls and via the corner portion of the correspondingactive trench portion 143. The lead-out portion 166 a is continuous tothe body region 141 at the side walls of the corresponding active trenchportion 143. A bottom portion of the lead-out portion 166 a ispositioned at the second main surface 104 side with respect to thebottom wall of the corresponding active trench portion 143.

A p type impurity concentration of the peripheral edge deep well region166 may be substantially equal to the p type impurity concentration ofthe body region 141. The p type impurity concentration of the peripheraledge deep well region 166 may exceed the p type impurity concentrationof the body region 141. The p type impurity concentration of theperipheral edge deep well region 166 may be less than the p typeimpurity concentration of the body region 141.

The p type impurity concentration of the peripheral edge deep wellregion 166 may be substantially equal to the p type impurityconcentration of each deep well region 165. The p type impurityconcentration of the peripheral edge deep well region 166 may exceed thep type impurity concentration of each deep well region 165. The p typeimpurity concentration of the peripheral edge deep well region 166 maybe less than the p type impurity concentration of each deep well region165.

The p type impurity concentration of the peripheral edge deep wellregion 166 may be not more than the p type impurity concentration of thecontact regions 164. The p type impurity concentration of the peripheraledge deep well region 166 may be less than the p type impurityconcentration of the contact regions 164. The p type impurityconcentration of the peripheral edge deep well region 166 may be notless than 1.0×10¹⁷ cm⁻³ and not more than 1.0×10¹⁹ cm⁻³.

With an SiC semiconductor device that includes just a pn junction diode,due to the structure being free from trenches, a problem ofconcentration of electric field inside the SiC semiconductor layer 102rarely occurs. The respective deep well regions 165 (the peripheral edgedeep well region 166) make the trench gate type MISFET approach thestructure of a pn junction diode. The electric field inside the SiCsemiconductor layer 102 can thereby be relaxed in the trench gate typeMISFET. Narrowing a pitch between the plurality of mutually adjacentdeep well regions 165 is thus effective in terms of relaxing theconcentration of electric field.

Also, with the respective deep well regions 165 having the bottomportions at the second main surface 104 side with respect to the bottomwalls of the corresponding gate trenches 142, concentration of electricfield with respect to the corresponding gate trenches 142 can be relaxedappropriately by the depletion layers. Preferably, distances between thebottom portions of the plurality of deep well regions 165 and the secondmain surface 104 are substantially equal.

Occurrence of variation in the distances between the bottom portions ofthe plurality of deep well regions 165 and the second main surface 104can thereby be suppressed. The withstand voltage (for example, anelectrostatic breakdown strength) of the SiC semiconductor layer 102 canthus be suppressed from being restricted by a configuration of therespective deep well regions 165 and therefore improvement of thewithstand voltage can be achieved appropriately.

By forming the source trenches 155, the p type impurity can beintroduced into the inner walls of the source trenches 155. Therespective deep well regions 165 can thereby be formed conformally tothe source trenches 155 and occurrence of variation in the depths of therespective deep well regions 165 can thus be suppressed appropriately.Also, by using the respective source trenches 155, the correspondingdeep well regions 165 can be formed appropriately in comparatively deepregions of the SiC semiconductor layer 102.

In this embodiment, the high concentration region 108 of the SiCepitaxial layer 107 is interposed in regions between the plurality ofmutually adjacent deep well regions 165. JFET (junction field effecttransistor) resistance can thereby be reduced in the regions between theplurality of mutually adjacent deep well regions 165.

Further, in this embodiment, the bottom portions of the respective deepwell regions 165 are positioned inside the high concentration region 108of the SiC epitaxial layer 107. Current paths can thereby be expanded inlateral direction parallel to the first main surface 103 from the bottomportions of the respective deep well regions 165. Current spreadresistance can thereby be reduced. The low concentration region 109 ofthe SiC epitaxial layer 107 increases the withstand voltage of the SiCsemiconductor layer 102 in such a structure.

Referring to FIG. 23, the SiC semiconductor device 101 includes a lowresistance electrode layer 167 formed on the gate electrode layers 149.Inside the respective gate trenches 142, the low resistance electrodelayer 167 covers the upper end portions of the gate electrode layers149. The low resistance electrode layer 167 includes a conductivematerial having a sheet resistance less than the sheet resistance of thegate electrode layers 149. The sheet resistance of the low resistanceelectrode layer 167 may be not less than 0.01Ω/□ and not more than10Ω/□.

The low resistance electrode layer 167 is formed in a film. The lowresistance electrode layer 167 has connection portions 167 a in contactwith the upper end portions of the gate electrode layers 149 andnon-connection portions 167 b opposite thereof. The connection portions167 a and the non-connection portions 167 b of the low resistanceelectrode layer 167 may be formed in curved shapes conforming to theupper end portions of the gate electrode layers 149. The connectionportions 167 a and the non-connection portions 167 b of the lowresistance electrode layer 167 may take on any of variousconfigurations.

An entirety of each connection portion 167 a may be positioned higherthan the first main surface 103. The entirety of the connection portion167 a may be positioned lower than the first main surface 103. Theconnection portion 167 a may include a portion positioned higher thanthe first main surface 103. The connection portion 167 a may include aportion positioned lower than the first main surface 103. For example, acentral portion of the connection portion 167 a may be positioned lowerthan the first main surface 103 and a peripheral edge portion of theconnection portion 167 a may be positioned higher than the first mainsurface 103.

An entirety of each non-connection portion 167 b may be positionedhigher than the first main surface 103. The entirety of thenon-connection portion 167 b may be positioned lower than the first mainsurface 103. The non-connection portion 167 b may include a portionpositioned higher than the first main surface 103. The non-connectionportion 167 b may include a portion positioned lower than the first mainsurface 103. For example, a central portion of the non-connectionportion 167 b may be positioned lower than the first main surface 103and a peripheral edge portion of the non-connection portion 167 b may bepositioned higher than the first main surface 103.

The low resistance electrode layer 167 has edge portions 167 ccontacting the gate insulating layer 148. Each edge portion 167 ccontacts a corner portion of the gate insulating layer 148 connectingthe corresponding first region 148 a and the corresponding second region148 b. The edge portion 167 c contacts the corresponding third region148 c of the gate insulating layer 148. More specifically, the edgeportion 167 c contacts the corresponding bulging portion 148 d of thegate insulating layer 148.

The edge portion 167 c is formed in a region at the first main surface103 side with respect to the bottom portions of the source regions 163.The edge portion 167 c is formed in a region further to the first mainsurface 103 side than boundary regions between the body region 141 andthe source regions 163. The edge portion 167 c thus opposes the sourceregions 163 across the gate insulating layer 148. The edge portion 167 cdoes not oppose the body region 141 across the gate insulating layer148.

Forming of a current path in a region of the gate insulating layer 148between the low resistance electrode layer 167 and the body region 141can thereby be suppressed. The current path may be formed by undesireddiffusion of an electrode material of the low resistance electrode layer167 into the gate insulating layer 148. In particular, a design wherethe edge portion 167 c is connected to the comparatively thick thirdregion 148 c of the gate insulating layer 148 (the corner portion of thegate insulating layer 148) is effective for reducing the risk of formingthe current path.

In the normal direction Z, a thickness Tr of the low resistanceelectrode layer 167 is not more than a thickness TG of the gateelectrode layer 149 (Tr≤TG). The thickness Tr of the low resistanceelectrode layer 167 is preferably less than the thickness TG of the gateelectrode layer 149 (Tr<TG). More specifically, the thickness Tr of thelow resistance electrode layer 167 is not more than one-half thethickness TG of the gate electrode layer 149 (Tr≤TG/2).

A ratio Tr/TG of the thickness Tr of the low resistance electrode layer167 with respect to the thickness TG of the gate electrode layer 149 isnot less than 0.01 and not more than 1. The thickness TG of the gateelectrode layer 149 may be not less than 0.5 μm and not more than 3 μm.The thickness Tr of the low resistance electrode layer 167 may be notless than 0.01 μm and not more than 3 μm.

A current supplied into the respective gate trenches 142 flows throughthe low resistance electrode layer 167 having the comparatively lowsheet resistance and is transmitted to entireties of the gate electrodelayers 149. The entireties of the gate electrode layers 149 (an entirearea of the active region 111) can thereby be made to transition rapidlyfrom an off state to an on state and therefore delay of switchingresponse can be suppressed.

In particular, although time is required for transmission of current ina case of the gate trenches 142 having a length of the millimeter order(a length not less than 1 mm), the delay of the switching response canbe suppressed appropriately by the low resistance electrode layer 167.That is, the low resistance electrode layer 167 is formed in a currentdiffusing electrode layer that diffuses the current into thecorresponding gate trench 142.

Also, as refinement of cell structure progresses, the width, depth,cross-sectional area, etc., of the gate electrode layer 149 decreasesand there is thus concern for the delay of the switching response due toincrease of electrical resistance inside each gate trench 142. In thisrespect, according to the low resistance electrode layer 167, theentireties of the gate electrode layers 149 can be made to transitionrapidly from the off state to the on state and therefore the delay ofthe switching response due to refinement can be suppressedappropriately.

Referring to FIG. 22, in this embodiment, the low resistance electrodelayer 167 also covers the upper end portion of the gate wiring layer150. A portion of the low resistance electrode layer 167 that covers theupper end portion of the gate wiring layer 150 is formed integral toportions of the low resistance electrode layer 167 covering the upperend portions of the gate electrode layers 149. The low resistanceelectrode layer 167 thereby covers entire areas of the gate electrodelayers 149 and an entire area of the gate wiring layer 150.

A current supplied from the gate pad 116 and the gate fingers 117 and118 to the gate wiring layer 150 is thus transmitted via the lowresistance electrode layer 167 having the comparatively low sheetresistance to the entireties of the gate electrode layers 149 and thegate wiring layer 150.

The entireties of the gate electrode layers 149 (the entire area of theactive region 111) can thereby be made to transition rapidly from theoff state to the on state via the gate wiring layer 150 and thereforethe delay of the switching response can be suppressed. In particular, inthe case of the gate trenches 142 having the length of the millimeterorder, the delay of the switching response can be suppressedappropriately by the low resistance electrode layer 167 covering theupper end portion of the gate wiring layer 150.

The low resistance electrode layer 167 includes a polycide layer. Thepolycide layer is formed by portions forming surface layer portions ofthe gate electrode layers 149 being silicided by a metal material. Morespecifically, the polycide layer is constituted of a p type polycidelayer that includes the p type impurity doped in the gate electrodelayers 149 (p type polysilicon). The polycide layer preferably has aspecific resistance of not less than 10 μΩ·cm and not more than 110μΩ·cm.

A sheet resistance inside the gate trench 142 embedded with the gateelectrode layers 149 and the low resistance electrode layer 167 is notmore than a sheet resistance of the gate electrode layers 149 alone. Thesheet resistance inside the gate trench 142 is preferably not more thana sheet resistance of an n type polysilicon doped with an n typeimpurity.

The sheet resistance inside the gate trench 142 is approximated by thesheet resistance of the low resistance electrode layer 167. That is, thesheet resistance inside the gate trench 142 may be not less than 0.01Ω/□and not more than 10Ω/□. The sheet resistance inside the gate trench 142is preferably less than 10Ω/□.

The low resistance electrode layer 167 may include at least one type ofmaterial among TiSi, TiSi₂, NiSi, CoSi, CoSi₂, MoSi₂, and WSi₂. Amongthese types of materials, NiSi, CoSi₂, and TiSi₂ are especially suitableas the polycide layer forming the low resistance electrode layer 167 dueto being comparatively low in specific resistance value and temperaturedependence.

The SiC semiconductor device 101 includes source sub-trenches 168 formedin regions of the first main surface 103 along the upper end portions ofthe source electrode layers 157 such as to be in communication with thecorresponding source trenches 155. Each source sub-trench 168 forms aportion of the side walls of the corresponding source trench 155.

In this embodiment, the source sub-trench 168 is formed in an endlessshape (a quadrilateral annular shape in this embodiment) surrounding theupper end portion of the source electrode layer 157 in plan view. Thesource sub-trench 168 borders the upper end portion of the sourceelectrode layer 157.

The source sub-trench 168 is formed by digging into a portion of thesource insulating layer 156. More specifically, the source sub-trench168 is formed by digging into the upper end portion of the sourceinsulating layer 156 and the upper end portion of the source electrodelayer 157 from the first main surface 103.

The upper end portion of the source electrode layer 157 has a shape thatis inwardly constricted with respect to a lower end portion of thesource electrode layer 157. The lower end portion of the sourceelectrode layer 157 is a portion of the source electrode layer 157 thatis positioned at the bottom wall side of the corresponding source trench155. A first direction width of the upper end portion of the sourceelectrode layer 157 may be less than a first direction width of thelower end portion of the source electrode layer 157.

The source sub-trench 168 is formed, in sectional view, to a convergentshape with a bottom area being less than an opening area. A bottom wallof the source sub-trench 168 may be formed in a curved shape toward thesecond main surface 104.

An Inner wall of the source sub-trench 168 exposes the source region163, the contact region 164, the source insulating layer 156, and thesource electrode layer 157. The inner wall of the source sub-trench 168exposes the first surface layer region 164 a and the second surfacelayer region 164 b of the contact region 164. The bottom wall of thesource sub-trench 168 exposes at least the first region 156 a of thesource insulating layer 156. An upper end portion of the first region156 a of the source insulating layer 156 is positioned lower than thefirst main surface 103.

An opening edge portion 169 of each source trench 155 includes aninclined portion 170 that inclines downwardly from the first mainsurface 103 toward an inner side of the source trench 155. The openingedge portion 169 of each source trench 155 is a corner portionconnecting the first main surface 103 and the side walls of the sourcetrench 155. The inclined portion 170 of each source trench 155 is formedby the source sub-trench 168.

In this embodiment, the inclined portion 170 is formed in a curved shaperecessed toward the SiC semiconductor layer 102 side. The inclinedportion 170 may be formed in a curved shape protruding toward the sourcesub-trench 168 side. The inclined portion 170 relaxes concentration ofelectric field with respect to the opening edge portion 169 of thecorresponding source trench 155.

Referring to FIG. 24 and FIG. 25, the active region 111 has an activemain surface 171 forming a portion of the first main surface 103. Theouter region 112 has an outer main surface 172 forming a portion of thefirst main surface 103. In this embodiment, the outer main surface 172is connected to the side surfaces 105A to 105D of the SiC semiconductorlayer 102.

The active main surface 171 and the outer main surface 172 respectivelyface the c-plane of the SiC monocrystal. Also, active main surface 171and the outer main surface 172 respectively each have the off angle θinclined in the [11-20] direction with respect to the c-planes of theSiC monocrystal.

The outer main surface 172 is positioned at the second main surface 104side with respect to the active main surface 171. In this embodiment,the outer region 112 is formed by digging into the first main surface103 toward the second main surface 104 side. The outer main surface 172is thus formed in a region that is recessed toward the second mainsurface 104 side with respect to the active main surface 171.

The outer main surface 172 may be positioned at the second main surface104 side with respect to the bottom walls of the respective gatetrenches 142. The outer main surface 172 may be formed at a depthposition substantially equal to the bottom walls of the respectivesource trenches 155. The outer main surface 172 may be positioned onsubstantially the same plane as the bottom walls of the respectivesource trenches 155.

A distance between the outer main surface 172 and the second mainsurface 104 may be substantially equal to distances between the bottomwalls of the respective source trenches 155 and the second main surface104. The outer main surface 172 may be positioned at the second mainsurface 104 side with respect to the bottom walls of the respectivesource trenches 155. The outer main surface 172 may be positioned at arange of not less than 0 μm and not more than 1 μm to the second mainsurface 104 side with respect to the bottom walls of the respectivesource trenches 155.

The outer main surface 172 exposes the SiC epitaxial layer 107. Morespecifically, the outer main surface 172 exposes the high concentrationregion 108 of the SiC epitaxial layer 107. The outer main surface 172thereby opposes the low concentration region 109 across the highconcentration region 108.

In this embodiment, the active region 111 is demarcated as a mesa by theouter region 112. That is, the active region 111 is formed as an activemesa 173 of mesa shape protruding further upward than the outer region112.

The active mesa 173 includes active side walls 174 connecting the activemain surface 171 and the outer main surface 172. The active side walls174 demarcate a boundary region between the active region 111 and theouter region 112. The first main surface 103 is formed by the activemain surface 171, the outer main surface 172, and the active side walls174.

In this embodiment, the active side walls 174 extend along the normaldirection Z to the active main surface 171 (outer main surface 172). Theactive side walls 174 are formed by the m-planes and the a-planes of theSiC monocrystal.

The active side walls 174 may have inclined surfaces inclined downwardlyfrom the active main surface 171 toward the outer main surface 172. Aninclination angle of each active side wall 174 is an angle that theactive side wall 174 forms with the active main surface 171 inside theSiC semiconductor layer 102.

In this case, the inclination angle of the active side wall 174 mayexceed 90° and be not more than 135°. The inclination angle of theactive side wall 174 may exceed 90° and be not more than 95°, be notless than 95° and not more than 100°, be not less than 100° and not morethan 110°, be not less than 110° and not more than 120°, or be not lessthan 120° and be not more than 135°. The inclination angle of the activeside wall 174 preferably exceeds 90° and is not more than 95°.

The active side walls 174 expose the SiC epitaxial layer 107. Morespecifically, the active side walls 174 expose the high concentrationregion 108. In a region at the active main surface 171 side, the activeside walls 174 expose at least the body region 141. In FIG. 24 and FIG.25, a configuration example where the active side walls 174 expose thebody region 141 and the source regions 163 is shown.

The SiC semiconductor device 101 includes a p⁺ type diode region 181(impurity region) formed in a surface layer portion of the outer mainsurface 172. Also, the SiC semiconductor device 101 includes a p typeouter deep well region 182 formed in the surface layer portion of theouter main surface 172. Also, the SiC semiconductor device 101 includesa p type field limit structure 183 formed in the surface layer portionof the outer main surface 172.

The diode region 181 is formed in a region of the outer region 112between the active side walls 174 and the side surfaces 105A to 105D.The diode region 181 is formed at intervals from the active side walls174 and the side surfaces 105A to 105D.

The diode region 181 extends in a band shape along the active region 111in plan view. In this embodiment, the diode region 181 is formed in anendless shape (a quadrilateral annular shape in this embodiment)surrounding the active region 111 in plan view. The diode region 181overlaps with the source routing wiring 123 in plan view. The dioderegion 181 is electrically connected to the source routing wiring 123.The diode region 181 forms a portion of the avalanche current absorbingstructure.

The diode region 181 forms a pn junction portion with the SiCsemiconductor layer 102. More specifically, the diode region 181 ispositioned inside the SiC epitaxial layer 107. The diode region 181 thusforms the pn junction portion with the SiC epitaxial layer 107.

Even more specifically, the diode region 181 is positioned inside thehigh concentration region 108. The diode region 181 thus forms the pnjunction portion with the high concentration region 108. A pn junctiondiode Dpn, having the diode region 181 as an anode and the SiCsemiconductor layer 102 as a cathode, is thereby formed.

An entirety of the diode region 181 is positioned at the second mainsurface 104 side with respect to the bottom walls of the respective gatetrenches 142. A bottom portion of the diode region 181 is positioned atthe second main surface 104 side with respect to the bottom walls of therespective source trenches 155. The bottom portion of the diode region181 may be formed at a depth position substantially equal to the bottomportions of the contact regions 164. The bottom portion of the dioderegion 181 may be positioned on substantially the same plane as thebottom portions of the contact regions 164.

A p type impurity concentration of the diode region 181 is substantiallyequal to the p type impurity concentration of the contact regions 164.The p type impurity concentration of the diode region 181 is greaterthan the p type impurity concentration of the body region 141. The ptype impurity concentration of the diode region 181 may be not less than1.0×10¹⁸ cm⁻³ and not more than 1.0×10²¹ cm⁻³.

The outer deep well region 182 is formed in a region between the activeside walls 174 and the diode region 181 in plan view. In thisembodiment, the outer deep well region 182 is formed at intervals towardthe diode region 181 side from the active side walls 174. The outer deepwell region 182 is also referred to as a withstand voltage adjustmentregion (withstand voltage holding region) that adjusts the withstandvoltage of the SiC semiconductor layer 102.

The outer deep well region 182 extends in a band shape along the activeregion 111 in plan view. In this embodiment, the outer deep well region182 is formed in an endless shape (a quadrilateral annular shape in thisembodiment) surrounding the active region 111 in plan view. The outerdeep well region 182 is electrically connected to the source routingwiring 123 via the diode region 181. The outer deep well region 182 mayform a portion of the pn junction diode Dpn. The outer deep well region182 may form a portion of the avalanche current absorbing structure.

An entirety of the outer deep well region 182 is positioned at thesecond main surface 104 side with respect to the bottom walls of therespective gate trenches 142. A bottom portion of the outer deep wellregion 182 is positioned at the second main surface 104 side withrespect to the bottom walls of the respective source trenches 155. Thebottom portion of the outer deep well region 182 is positioned at thesecond main surface 104 side with respect to the bottom portion of thediode region 181.

The bottom portion of the outer deep well region 182 may be formed at adepth position substantially equal to the bottom portions of therespective deep well regions 165. The bottom portion of the outer deepwell region 182 may be positioned on substantially the same plane as thebottom portions of the respective deep well regions 165. A distancebetween the bottom portion of the outer deep well region 182 and theouter main surface 172 may be substantially equal to distances betweenthe bottom portions of the respective deep well regions 165 and thebottom walls of the respective source trenches 155.

A distance between the bottom portion of the outer deep well region 182and the second main surface 104 may be substantially equal to thedistances between the bottom portions of the respective deep wellregions 165 and the second main surface 104. Variation can thereby besuppressed from occurring between the distance between the bottomportion of the outer deep well region 182 and the second main surface104 and the distances between the bottom portions of the respective deepwell regions 165 and the second main surface 104.

The withstand voltage (for example, the electrostatic breakdownstrength) of the SiC semiconductor layer 102 can thus be suppressed frombeing restricted by the configuration of the outer deep well region 182and the configuration of the respective deep well regions 165 andtherefore improvement of the withstand voltage can be achievedappropriately.

The bottom portion of the outer deep well region 182 may be positionedat the second main surface 104 side with respect to the bottom portionsof the respective deep well regions 165. The bottom portion of the outerdeep well region 182 may be positioned at a range of not less than 0 μmand not more than 1 μm to the second main surface 104 side with respectto the bottom portions of the respective deep well regions 165.

An inner peripheral edge of the outer deep well region 182 may extend tothe vicinity of the boundary region between the active region 111 andthe outer region 112. The outer deep well region 182 may cross theboundary region between the active region 111 and the outer region 112.The inner peripheral edge of the outer deep well region 182 may covercorner portions connecting the active side walls 174 and the outer mainsurface 172. The inner peripheral edge of the outer deep well region 182may extend further along the active side walls 174 and be connected tothe body region 141.

In this embodiment, an outer peripheral edge of the outer deep wellregion 182 covers the diode region 181 from the second main surface 104side. The outer deep well region 182 may overlap with the source routingwiring 123 in plan view. The outer peripheral edge of the outer deepwell region 182 may be formed at intervals toward the active side wall174 sides from the diode region 181.

A p type impurity concentration of the outer deep well region 182 may benot more than the p type impurity concentration of the diode region 181.The p type impurity concentration of the outer deep well region 182 maybe less than the p type impurity concentration of the diode region 181.

The p type impurity concentration of the outer deep well region 182 maybe substantially equal to the p type impurity concentration of each deepwell region 165. The p type impurity concentration of the outer deepwell region 182 may be substantially equal to the p type impurityconcentration of the body region 141.

The p type impurity concentration of the outer deep well region 182 mayexceed the p type impurity concentration of the body region 141. The ptype impurity concentration of the outer deep well region 182 may beless than the p type impurity concentration of the body region 141.

The p type impurity concentration of the outer deep well region 182 maybe not more than the p type impurity concentration of each contactregion 164. The p type impurity concentration of the outer deep wellregion 182 may be less than the p type impurity concentration of eachcontact region 164. The p type impurity concentration of the outer deepwell region 182 may be not less than 1.0×10¹⁷ cm⁻³ and not more than1.0×10¹⁹ cm⁻³.

The field limit structure 183 is formed in a region between the dioderegion 181 and the side surfaces 105A to 105D in plan view. In thisembodiment, the field limit structure 183 is formed at intervals towardthe diode region 181 side from the side surfaces 105A to 105D.

The field limit structure 183 includes one or a plurality of (forexample, not less than two and not more than twenty) field limit regions184. In this embodiment, the field limit structure 183 includes a fieldlimit region group having a plurality of (five) field limit regions184A, 184B, 184C, 184D, and 184E. The field limit regions 184A to 184Eare formed in that order at intervals along a direction away from thediode region 181.

The field limit regions 184A to 184E respectively extend in band shapesalong the peripheral edge of the active region 111 in plan view. Morespecifically, the field limit regions 184A to 184E are respectivelyformed in endless shapes (quadrilateral annular shapes in thisembodiment) surrounding the active region 111 in plan view. Each of thefield limit regions 184A to 184E is also referred to as an FLR (fieldlimiting ring) region.

In this embodiment, bottom portions of the field limit regions 184A to184E are positioned at the second main surface 104 side with respect tothe bottom portion of the diode region 181. In this embodiment, thefield limit region 184A at an innermost side among the field limitregions 184A to 184E covers the diode region 181 from the second mainsurface 104 side. The field limit region 184A may be overlapped in planview with the source routing wiring 123 described above.

The field limit region 184A is electrically connected to the sourcerouting wiring 123 via the diode region 181. The field limit region 184Amay form a portion of the pn junction diode Dpn. The field limit region184A may form a portion of the avalanche current absorbing structure.

Entireties of the field limit regions 184A to 184E are positioned at thesecond main surface 104 side with respect to the bottom walls of therespective gate trenches 142. The bottom portions of the field limitregions 184A to 184E are positioned at the second main surface 104 sidewith respect to the bottom walls of the respective source trenches 155.

The field limit regions 184A to 184E may be formed at a depth positionsubstantially equal to the respective deep well regions 165 (the outerdeep well region 182). The bottom portions of the field limit regions184A to 184E may be positioned on substantially the same plane as thebottom portions of the respective deep well regions 165 (the outer deepwell region 182).

The bottom portions of the field limit regions 184A to 184E may bepositioned at the outer main surface 172 side with respect to the bottomportions of the respective deep well regions 165 (the outer deep wellregion 182). The bottom portions of the field limit regions 184A to 184Emay be positioned at the second main surface 104 side with respect tothe bottom portions of the respective deep well regions 165 (the outerdeep well region 182).

Widths between mutually adjacent field limit regions 184A to 184E maydiffer from each other. The widths between mutually adjacent field limitregions 184A to 184E may increase in a direction away from the activeregion 111. The widths between mutually adjacent field limit regions184A to 184E may decrease in the direction away from the active region111.

Depths of the field limit regions 184A to 184E may differ from eachother. The depths of the field limit regions 184A to 184E may decreasein the direction away from the active region 111. The depths of thefield limit regions 184A to 184E may increase in the direction away fromthe active region 111.

A p type impurity concentration of the field limit regions 184A to 184Emay be not more than the p type impurity concentration of the dioderegion 181. The p type impurity concentration of the field limit regions184A to 184E may be less than the p type impurity concentration of thediode region 181.

The p type impurity concentration of the field limit regions 184A to184E may be not more than the p type impurity concentration of the outerdeep well region 182. The p type impurity concentration of the fieldlimit regions 184A to 184E may be less than the p type impurityconcentration of the outer deep well region 182.

The p type impurity concentration of the field limit regions 184A to184E may be not less than the p type impurity concentration of the outerdeep well region 182. The p type impurity concentration of the fieldlimit regions 184A to 184E may be greater than the p type impurityconcentration of the outer deep well region 182.

The p type impurity concentration of the field limit regions 184A to184E may be not less than 1.0×10¹⁵ cm⁻³ and not more than 1.0×10¹⁸ cm⁻³.Preferably, the p type impurity concentration of the diode region181>the p type impurity concentration of the outer deep well region182>the p type impurity concentration of the field limit regions 184A to184E.

The field limit structure 183 relaxes concentration of electric field inthe outer region 112. The number, widths, depths, p type impurityconcentration, etc., of the field limit regions 184 may take on any ofvarious values in accordance with the electric field to be relaxed.

With this embodiment, an example where the field limit structure 183includes one or a plurality of field limit regions 184 formed in theregion between the diode region 181 and the side surfaces 105A to 105Din plan view was described.

However, the field limit structure 183 may include one or a plurality offield limit regions 184 formed in the region between the active sidewalls 174 and the diode region 181 in plan view in place of the regionbetween the diode region 181 and the side surfaces 105A to 105D.

Also, the field limit structure 183 may include one or a plurality offield limit regions 184 formed in the region between the diode region181 and the side surfaces 105A to 105D in plan view and one or aplurality of field limit regions 184 formed in the region between theactive side walls 174 and the diode region 181 in plan view.

The SiC semiconductor device 101 includes an outer insulating layer 191formed on the first main surface 103 in the outer region 112. The outerinsulating layer 191 forms a portion of the main surface insulatinglayer 113. The outer insulating layer 191 forms portions of theinsulating side surfaces 114A to 114D of the main surface insulatinglayer 113.

The outer insulating layer 191 selectively covers the diode region 181,the outer deep well region 182, and the field limit structure 183 in theouter region 112. The outer insulating layer 191 is formed in a filmalong the active side walls 174 and the outer main surface 172. On theactive main surface 171, the outer insulating layer 191 is continuous tothe gate insulating layer 148. More specifically, the outer insulatinglayer 191 is continuous to the third regions 148 c of the gateinsulating layer 148.

The outer insulating layer 191 may include silicon oxide. The outerinsulating layer 191 may include another insulating film of siliconnitride, etc. In this embodiment, the outer insulating layer 191 isformed of the same insulating material type as the gate insulating layer148.

The outer insulating layer 191 includes a first region 191 a and asecond region 191 b. The first region 191 a of the outer insulatinglayer 191 covers the active side walls 174. The second region 191 b ofthe outer insulating layer 191 covers the outer main surface 172.

A thickness of the second region 191 b of the outer insulating layer 191may be not more than a thickness of the first region 191 a of the outerinsulating layer 191. The thickness of the second region 191 b of theouter insulating layer 191 may be less than the thickness of the firstregion 191 a of the outer insulating layer 191.

The thickness of the first region 191 a of the outer insulating layer191 may be substantially equal to the thickness of the first regions 191a of the gate insulating layer 148. The thickness of the second region191 b of the outer insulating layer 191 may be substantially equal tothe thickness of the third regions 148 c of the gate insulating layer148. Obviously, the outer insulating layer 191 having a uniformthickness may be formed.

Referring to FIG. 24 and FIG. 25, the SiC semiconductor device 101further includes a side wall structure 192 covering the active sidewalls 174. The side wall structure 192 protects and reinforces theactive mesa 173 from the outer region 112 side.

Also, the side wall structure 192 forms a level difference moderatingstructure that moderates a level difference formed between the activemain surface 171 and the outer main surface 172. If an upper layerstructure (covering layer) covering the boundary region between theactive region 111 and the outer region 112 is formed, the upper layerstructure covers the side wall structure 192. The side wall structure192 improves flatness of the upper layer structure.

The side wall structure 192 may have an inclined portion 193 thatinclines downwardly from the active main surface 171 toward the outermain surface 172. The level difference can be moderated appropriately bythe inclined portion 193. The inclined portion 193 may be formed in acurved shape recessed toward the SiC semiconductor layer 102 side. Theinclined portion 193 may be formed in a curved shape protruding in adirection away from the SiC semiconductor layer 102.

The inclined portion 193 may extend in a plane from the active mainsurface 171 side toward the outer main surface 172 side. The inclinedportion 193 may extend rectilinearly from the active main surface 171side toward the outer main surface 172 side.

The inclined portion 193 may be formed in a set of stairs descendingfrom the active main surface 171 toward the outer main surface 172. Thatis, the inclined portion 193 may have one or a plurality of stepportions recessed toward the SiC semiconductor layer 102 side. Aplurality of step portions increase a surface area of the inclinedportion 193 and improve adhesion force with respect to the upper layerstructure.

The inclined portion 193 may include a plurality of raised portionsraised in the direction away from the SiC semiconductor layer 102. Theplurality of raised portions increase the surface area of the inclinedportion 193 and improve the adhesion force with respect to the upperlayer structure. The inclined portion 193 may include a plurality ofrecesses recessed toward the SiC semiconductor layer 102 side. Theplurality of recesses increase the surface area of the inclined portion193 and improve the adhesion force with respect to the upper layerstructure.

The side wall structure 192 is formed self-aligningly with respect tothe active main surface 171. More specifically, the side wall structure192 is formed along the active side walls 174. In this embodiment, theside wall structure 192 is formed in an endless shape (a quadrilateralannular shape in this embodiment) surrounding the active region 111 inplan view.

The side wall structure 192 preferably includes a p type polysilicondoped with a p type impurity. In this case, the side wall structure 192can be formed at the same time as the gate electrode layers 149 and thesource electrode layers 157.

A p type impurity concentration of the side wall structure 192 is notless than the p type impurity concentration of the body region 141. Morespecifically, the p type impurity concentration of the side wallstructure 192 is greater than the p type impurity concentration of thebody region 141. The p type impurity of the side wall structure 192 mayinclude at least one type of material among boron (B), aluminum (Al),indium (In), and gallium (Ga).

The p type impurity concentration of the side wall structure 192 may benot less than 1×10¹⁸ cm⁻³ and not more than 1×10²² cm⁻³. A sheetresistance of the side wall structure 192 may be not less than 10Ω/□ andnot more than 500Ω/□ (approximately 200Ω/□ in this embodiment). The ptype impurity concentration of the side wall structure 192 may besubstantially equal to the p type impurity concentration of the gateelectrode layers 149. The sheet resistance of the side wall structure192 may be substantially equal to the sheet resistance of the gateelectrode layers 149.

The side wall structure 192 may include an n type polysilicon in placeof or in addition to the p type polysilicon. The side wall structure 192may include at least one type of material among tungsten, aluminum,copper, an aluminum alloy, and a copper alloy in place of or in additionto the p type polysilicon. The side wall structure 192 may include aninsulating material. In this case, an insulating property of the activeregion 111 with respect to the outer region 112 can be improved by theside wall structure 192.

Referring to FIG. 21 to FIG. 25, the SiC semiconductor device 101includes an interlayer insulating layer 201 formed on the first mainsurface 103. The interlayer insulating layer 201 forms a portion of themain surface insulating layer 113. The interlayer insulating layer 201forms portions of the insulating side surfaces 114A to 114D of the mainsurface insulating layer 113. That is, the main surface insulating layer113 has a laminated structure that includes the gate insulating layer148 (outer insulating layer 191) and the interlayer insulating layer201.

The interlayer insulating layer 201 selectively covers the active region111 and the outer region 112. More specifically, the interlayerinsulating layer 201 selectively covers the third regions 148 c of thegate insulating layer 148 and the outer insulating layer 191.

The interlayer insulating layer 201 is formed in a film along the activemain surface 171 and the outer main surface 172. In the active region111, the interlayer insulating layer 201 selectively covers the trenchgate structures 161, the gate wiring layer 150, and the trench sourcestructures 162. In the outer region 112, the interlayer insulating layer201 selectively covers the diode region 181, the outer deep well region182, and the field limit structure 183.

In the boundary region between the active region 111 and the outerregion 112, the interlayer insulating layer 201 is formed along an outersurface (inclined portion 193) of the side wall structure 192. Theinterlayer insulating layer 201 forms a portion of the upper layerstructure that covers the side wall structure 192.

The interlayer insulating layer 201 may include silicon oxide or siliconnitride. The interlayer insulating layer 201 may include PSG (phosphorsilicate glass) and/or BPSG (boron phosphor silicate glass) as anexample of silicon oxide. The interlayer insulating layer 201 may have alaminated structure including a PSG layer and a BPSG layer laminated inthat order from the first main surface 103 side. The interlayerinsulating layer 201 may have a laminated structure including a BPSGlayer and a PSG layer laminated in that order from the first mainsurface 103 side.

The interlayer insulating layer 201 includes a gate contact hole 202,source contact holes 203, and a diode contact hole 204. The interlayerinsulating layer 201 also includes an anchor hole 205.

The gate contact hole 202 exposes the gate wiring layer 150 in theactive region 111. The gate contact hole 202 may be formed in a bandshape oriented along the gate wiring layer 150. An opening edge portionof the gate contact hole 202 is formed in a curved shape toward the gatecontact hole 202 side.

The source contact holes 203 expose the source regions 163, the contactregions 164, and the trench source structures 162 in the active region111. The source contact holes 203 may be formed in band shapes orientedalong the trench source structures 162, etc. An opening edge portion ofeach source contact hole 203 is formed in a curved shape toward thesource contact hole 203 side.

The diode contact hole 204 exposes the diode region 181 in the outerregion 112. The diode contact hole 204 may be formed in a band shape(more specifically, an endless shape) extending along the diode region181.

The diode contact hole 204 may expose the outer deep well region 182and/or the field limit structure 183. An opening edge portion of thediode contact hole 204 is formed in a curved shape toward the diodecontact hole 204 side.

The anchor hole 205 is formed by digging into the interlayer insulatinglayer 201 in the outer region 112. The anchor hole 205 is formed in theregion between the diode region 181 and the side surfaces 105A to 105Din plan view. More specifically, the anchor hole 205 is formed in aregion between the field limit structure 183 and the side surfaces 105Ato 105D in plan view. The anchor hole 205 exposes the first main surface103 (outer main surface 172). An opening edge portion of the anchor hole205 is formed in a curved shape toward the anchor hole 205 side.

Referring to FIG. 19, the anchor hole 205 extends in a band shape alongthe active region 111 in plan view. In this embodiment, the anchor hole205 is formed in an endless shape (a quadrilateral annular shape in thisembodiment) surrounding the active region 111 in plan view.

In this embodiment, a single anchor hole 205 is formed in a portion ofthe interlayer insulating layer 201 covering the outer region 112.However, a plurality of anchor holes 205 may be formed in portions ofthe interlayer insulating layer 201 covering the outer region 112.

The main surface gate electrode layer 115 and the main surface sourceelectrode layer 121 described above are respectively formed on theinterlayer insulating layer 201. Each of the main surface gate electrodelayer 115 and the main surface source electrode layer 121 has alaminated structure that includes a barrier electrode layer 206 and amain electrode layer 207 laminated in that order from the SiCsemiconductor layer 102 side.

The barrier electrode layer 206 may have a single layer structureconstituted of a titanium layer or a titanium nitride layer. The barrierelectrode layer 206 may have a laminated structure including a titaniumlayer and a titanium nitride layer that are laminated in that order fromthe SiC semiconductor layer 102 side.

A thickness of the main electrode layer 207 exceeds a thickness of thebarrier electrode layer 206. The main electrode layer 207 includes aconductive material having a resistance value less than a resistancevalue of the barrier electrode layer 206. The main electrode layer 207may include at least one type of material among aluminum, copper, analuminum alloy, and a copper alloy. The main electrode layer 207 mayinclude at least one type of material among an AlSi alloy, an AlSiCualloy, and an AlCu alloy. In this embodiment, the main electrode layer207 includes an AlSiCu alloy.

The outer gate finger 117 included in the main surface gate electrodelayer 115 enters into the gate contact hole 202 from on the interlayerinsulating layer 201. The outer gate finger 117 is electricallyconnected to the gate wiring layer 150 inside the gate contact hole 202.An electrical signal from the gate pad 116 is thereby transmitted to thegate electrode layers 149 via the outer gate finger 117.

The source pad 122 included in the main surface source electrode layer121 enters into the source contact holes 203 and the source sub-trenches168 from on the interlayer insulating layer 201. The source pad 122 iselectrically connected to the source regions 163, the contact regions164, and the source electrode layers 157 inside the source contact holes203 and the source sub-trenches 168.

The source electrode layers 157 may be formed using partial regions ofthe source pad 122. The source electrode layers 157 may be formed byportions of the source pad 122 entering into the respective sourcetrenches 155.

The source routing wiring 123 included in the main surface sourceelectrode layer 121 enters into the diode contact hole 204 from on theinterlayer insulating layer 201. The source routing wiring 123 iselectrically connected to the diode region 181 inside the diode contacthole 204.

The source connection portion 124 included in the main surface sourceelectrode layer 121 crosses the side wall structure 192 from the activeregion 111 and is led out to the outer region 112. The source connectionportion 124 forms a portion of the upper layer structure covering theside wall structure 192.

The passivation layer 125 described above is formed on the interlayerinsulating layer 201. The passivation layer 125 is formed in a filmalong the interlayer insulating layer 201. The passivation layer 125selectively covers the active region 111 and the outer region 112 viathe interlayer insulating layer 201.

The passivation layer 125 crosses the side wall structure 192 from theactive region 111 and is led out to the outer region 112. Thepassivation layer 125 forms a portion of the upper layer structurecovering the side wall structure 192.

Referring to FIG. 24, in the outer region 112, the passivation layer 125enters into the anchor hole 205 from on the interlayer insulating layer201. Inside the anchor hole 205, the passivation layer 125 is connectedto the outer main surface 172 (first main surface 103). A recess 211recessed in conformance to the anchor hole 205 is formed in a region ofan outer surface of the passivation layer 125 positioned on the anchorhole 205.

The resin layer 129 described above is formed on the passivation layer125. The resin layer 129 is formed in a film along the passivation layer125. The resin layer 129 selectively covers the active region 111 andthe outer region 112 across the passivation layer 125 and the interlayerinsulating layer 201. The resin layer 129 crosses the side wallstructure 192 from the active region 111 and is led out to the outerregion 112. The resin layer 129 forms a portion of the upper layerstructure covering the side wall structure 192.

Referring to FIG. 24, the resin layer 129 has, in the outer region 112,an anchor portion entering into the recess 211 of the passivation layer125. An anchor structure arranged to improve a connection strength ofthe resin layer 129 is thus formed in the outer region 112.

The anchor structure includes an uneven structure formed in the firstmain surface 103 in the outer region 112. More specifically, the unevenstructure (anchor structure) includes unevenness formed using theinterlayer insulating layer 201 covering the outer main surface 172.Even more specifically, the uneven structure (anchor structure) includesthe anchor hole 205 formed in the interlayer insulating layer 201.

The resin layer 129 is engaged with the anchor hole 205. In thisembodiment, the resin layer 129 is engaged with the anchor hole 205 viathe passivation layer 125. The connection strength of the resin layer129 with respect to the first main surface 103 can thereby be improvedand therefore, peeling of the resin layer 129 can be suppressed.

As described above, even with the SiC semiconductor device 101, the sameeffects as the effects described for the SiC semiconductor device 1 canbe exhibited. Also, with the SiC semiconductor device 101, depletionlayers can be spread from boundary regions (pn junction portions)between the SiC semiconductor layer 102 and the deep well regions 165toward regions at the second main surface 104 side with respect to thegate trenches 142.

Current paths of a short-circuit current flowing between the mainsurface source electrode layer 121 and the drain electrode layers 133can thereby be narrowed. Also, a feedback capacitance Crss can bereduced inverse-proportionately by the depletion layers spreading fromthe boundary regions between the SiC semiconductor layer 102 and thedeep well regions 165. The SiC semiconductor device 101 can thus beprovided in which the short-circuit capacity can be improved and thefeedback capacitance Crss can be reduced. The feedback capacitance Crssis a static capacitance across the gate electrode layers 149 and thedrain electrode layer 133.

The depletion layers spreading from the boundary regions between the SiCsemiconductor layer 102 and the deep well regions 165 may overlap withthe bottom walls of the gate trenches 142. In this case, the depletionlayers spreading from the bottom portions of the deep well regions 165may overlap with the bottom walls of the gate trenches 142.

Also, with the SiC semiconductor device 101, the distances between thebottom portions of the respective deep well regions 165 and the secondmain surface 104 are substantially equal. Occurrence of variation in thedistances between the bottom portions of the respective deep wellregions 165 and the second main surface 104 can thereby be suppressed.The withstand voltage (for example, the electrostatic breakdownstrength) of the SiC semiconductor layer 102 can thus be suppressed frombeing restricted by the deep well regions 165 and therefore improvementof the withstand voltage can be achieved appropriately.

Also, with the SiC semiconductor device 101, the diode region 181 isformed in the outer region 112. The diode region 181 is electricallyconnected to the main surface source electrode layer 121. The avalanchecurrent generated in the outer region 112 can thereby be made to flowinto the main surface source electrode layer 121 via the diode region181. That is, the avalanche current generated in the outer region 112can be absorbed by the diode region 181 and the main surface sourceelectrode layer 121. Consequently, stability of operation of the MISFETcan be improved.

Also, with the SiC semiconductor device 101, the outer deep well region182 is formed in the outer region 112. The withstand voltage of the SiCsemiconductor layer 102 can thereby be adjusted in the outer region 112.In particular, with the SiC semiconductor device 101, the outer deepwell region 182 is formed at substantially the same depth position asthe deep well regions 165. More specifically, the bottom portion of theouter deep well region 182 is positioned on substantially the same planeas the bottom portions of the deep well regions 165.

The distance between the bottom portion of the outer deep well region182 and the second main surface 104 is substantially equal to thedistances between the bottom portions of the deep well regions 165 andthe second main surface 104. Variation can thereby be suppressed fromoccurring between the distance between the bottom portion of the outerdeep well region 182 and the second main surface 104 and the distancesbetween the bottom portions of the deep well regions 165 and the secondmain surface 104.

The withstand voltage (for example, the electrostatic breakdownstrength) of the SiC semiconductor layer 102 can thus be suppressed frombeing restricted by the configuration of outer deep well region 182 andthe configuration of the deep well regions 165. Consequently,improvement of the withstand voltage can be achieved appropriately. Inparticular, with the SiC semiconductor device 101, the outer region 112is formed in a region at the second main surface 104 side with respectto the active region 111. The position of the bottom portion of theouter deep well region 182 can thereby be made to approach the positionsof the bottom portions of the deep well regions 165 appropriately.

That is, a need to introduce the p type impurity to a comparatively deepposition of the surface layer portion of the first main surface 103during the forming of the outer deep well region 182 is eliminated. Theposition of the bottom portion of the outer deep well region 182 canthus be suppressed appropriately from deviating greatly with respect tothe positions of the bottom portions of the deep well regions 165.

Moreover, with the SiC semiconductor device 101, the outer main surface172 is positioned on substantially the same plane as the bottom walls ofthe source trenches 155. Thereby, if the p type impurity is introducedinto the bottom walls of the source trenches 155 and the outer mainsurface 172 at an equal energy, the deep well regions 165 and the outerdeep well region 182 can be formed at substantially equal depthpositions. Consequently, the position of the bottom portion of the outerdeep well region 182 can be suppressed even more appropriately fromdeviating greatly with respect to the positions of the bottom portionsof the deep well regions 165.

Also, with the SiC semiconductor device 101, the field limit structure183 is formed in the outer region 112. An electric field relaxationeffect by the field limit structure 183 can thereby be obtained in theouter region 112. The electrostatic breakdown strength of the SiCsemiconductor layer 102 can thus be improved appropriately.

Also, with the SiC semiconductor device 101, the active region 111 isformed as the active mesa 173 of mesa shape. The active mesa 173includes the active side walls 174 connecting the active main surface171 of the active region 111 and the outer main surface 172. The leveldifference moderating structure that moderates the level differencebetween the active main surface 171 and the outer main surface 172 isformed in the region between the active main surface 171 and the outermain surface 172. The level difference moderating structure includes theside wall structure 192.

The level difference between the active main surface 171 and the outermain surface 172 can thereby be moderated appropriately. The flatness ofthe upper layer structure formed on the side wall structure 192 can thusbe improved appropriately. With the SiC semiconductor device 101, theinterlayer insulating layer 201, the main surface source electrode layer121, the passivation layer 125, and the resin layer 129 are formed as anexample of the upper layer structure.

Also, with the SiC semiconductor device 101, the anchor structurearranged to improve the connection strength of the resin layer 129 isformed in the outer region 112. The anchor structure includes the unevenstructure formed in the first main surface 103 in the outer region 112.More specifically, the uneven structure (anchor structure) includes theunevenness formed using the interlayer insulating layer 201 formed onthe first main surface 103 in the outer region 112. Even morespecifically, the uneven structure (anchor structure) includes theanchor hole 205 formed in the interlayer insulating layer 201.

The resin layer 129 is engaged with the anchor hole 205. In thisembodiment, the resin layer 129 is engaged with the anchor hole 205 viathe passivation layer 125. The connection strength of the resin layer129 with respect to the first main surface 103 can thereby be improvedand therefore, peeling of the resin layer 129 can be suppressedappropriately.

Also, with the SiC semiconductor device 101, the trench gate structures161 with each of which the gate electrode layer 149 is embedded acrossthe gate insulating layer 148 in the gate trench 142 are formed. Withthe trench gate structure 161, the gate electrode layer 149 is coveredby the low resistance electrode layer 167 in the limited space of thegate trench 142. An effect described using FIG. 26 can be exhibited bysuch a structure.

FIG. 26 is a graph for describing the sheet resistance inside the gatetrench 142. In FIG. 26, the ordinate represents sheet resistance (Ω/□)and the abscissa represents items. In FIG. 26, a first bar graph BL1, asecond bar graph BL2, and a third bar graph BL3 are shown.

The first bar graph BL1 represents the sheet resistance inside the gatetrench 142 embedded with the n type polysilicon. The second bar graphBL2 represents the sheet resistance inside the gate trench 142 embeddedwith the p type polysilicon.

The third bar graph BL3 represents the sheet resistance inside the gatetrench 142 embedded with the gate electrode layers 149 (p typepolysilicon) and the low resistance electrode layer 167. Here, a casewhere the low resistance electrode layer 167 constituted of TiSi₂ (ptype titanium silicide) as an example of polycide (silicide) is formedshall be described.

Referring to the first bar graph BL1, the sheet resistance inside thegate trench 142 embedded with the n type polysilicon was 10Ω/□.Referring to the second bar graph BL2, the sheet resistance inside thegate trench 142 embedded with the p type polysilicon was 200Ω/□.Referring to the third bar graph BL3, the sheet resistance inside thegate trench 142 embedded with the gate electrode layers 149 (p typepolysilicon) and the low resistance electrode layer 167 was 2Ω/□.

The p type polysilicon has a work function differing from the n typepolysilicon. With a structure in which the p type polysilicon isembedded in the gate trenches 142, a gate threshold voltage Vth can beincreased by approximately 1 V.

However, the p type polysilicon has a sheet resistance of several tensof times (here, approximately 20 times) higher than a sheet resistanceof the n type polysilicon. Therefore, if the p type polysilicon isadopted as a material of the gate electrode layers 149, energy lossincreases significantly in accompaniment with increase of parasiticresistance inside the gate trenches 142 (referred to hereinafter simplyas “gate resistance”).

On the other hand, with the structure having the low resistanceelectrode layer 167 on the gate electrode layers 149 (p typepolysilicon), the sheet resistance can be decreased to not more than1/100th in comparison to a case of not forming the low resistanceelectrode layer 167. That is, with the structure having the lowresistance electrode layer 167, the sheet resistance can be decreased tonot more than ⅕th in comparison to the gate electrode layers 149including the n type polysilicon.

Thus, with the structure having the low resistance electrode layer 167,the sheet resistance inside the gate trench 142 can be reduced whileincreasing the gate threshold voltage Vth (for example, increasing it byapproximately 1 V). Reduction of the gate resistance can thereby beachieved and therefore a current can be diffused efficiently along thetrench gate structures 161. Consequently, reduction of switching delaycan be achieved.

Also, with the structure having the low resistance electrode layer 167,the p type impurity concentration of the body region 141 and the p typeimpurity concentration of the contact regions 164 do not have to beincreased. The gate threshold voltage Vth can thus be increasedappropriately while suppressing the increase in channel resistance.

The low resistance electrode layer 167 may include at least one type ofmaterial among TiSi, TiSi₂, NiSi, CoSi, CoSi₂, MoSi₂, and WSi₂. Amongthese types of materials, NiSi, CoSi₂, and TiSi₂ are especially suitableas the polycide layer forming the low resistance electrode layer 167 dueto being comparatively low in the value of specific resistance andtemperature dependence.

As a result of further tests by the present inventors, increase ofgate-to-source leak current was observed during low electric fieldapplication when TiSi₂ was adopted as the material of the low resistanceelectrode layer 167. On the other hand, increase of gate-to-source leakcurrent was not observed during low electric field application whenCoSi₂ was adopted. In consideration of this point, it is considered thatCoSi₂ is most preferable as the polycide layer forming the lowresistance electrode layer 167.

Further, with the SiC semiconductor device 101, the gate wiring layer150 is covered by the low resistance electrode layer 167. Reduction ofgate resistance of the gate wiring layer 150 can also be achievedthereby. In particular, with the structure where the gate electrodelayers 149 and the gate wiring layer 150 are covered by the lowresistance electrode layer 167, the current can be diffused efficientlyalong the trench gate structures 161. The reduction of switching delaycan thus be achieved appropriately.

FIG. 27 is an enlarged view of a region corresponding to FIG. 20 and isan enlarged view of an SiC semiconductor device 221 according to afourth preferred embodiment of the present invention. FIG. 28 is asectional view taken along line XXVIII-XXVIII shown in FIG. 27. In thefollowing, structures corresponding to structures described with the SiCsemiconductor device 101 shall be provided with the same reference signsand description thereof shall be omitted.

Referring to FIG. 27 and FIG. 28, the SiC semiconductor device 221includes an outer gate trench 222 formed in the first main surface 103in the active region 111. The outer gate trench 222 extends in a bandshape along the peripheral edge portions of the active region 111. Theouter gate trench 222 is formed in a region of the first main surface103 directly below the outer gate finger 117.

The outer gate trench 222 extends along the outer gate finger 117. Morespecifically, the outer gate trench 222 is formed along the three sidesurfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 such asto demarcate the inner region of the active region 111 from threedirections. The outer gate trench 222 may be formed in an endless shape(for example, a quadrilateral annular shape) surrounding the innerregion of the active region 111.

The outer gate trench 222 is in communication with the contact trenchportions 144 of the respective gate trenches 142. The outer gate trench222 and the gate trenches 142 are thereby formed by a single trench.

The gate wiring layer 150 described above is embedded in the outer gatetrench 222. The gate wiring layer 150 is connected to the gate electrodelayers 149 at communication portions of the gate trenches 142 and theouter gate trench 222. Also, the low resistance electrode layer 167described above covers the gate wiring layer 150 inside the outer gatetrench 222. In this case, the low resistance electrode layer 167covering the gate electrode layers 149 and the low resistance electrodelayer 167 covering the gate wiring layer 150 are formed inside a singletrench.

As described above, even with the SiC semiconductor device 221, the sameeffects as the effects described for the SiC semiconductor device 101can be exhibited. Also, with the semiconductor device 221, the gatewiring layer 150 is not required to be led out onto the first mainsurface 103. The gate wiring layer 150 can thereby be suppressed fromopposing the SiC semiconductor layer 102 across the gate insulatinglayer 148 at the opening edge portions 146 of the gate trenches 142 (theouter gate trench 222). Consequently, the concentration of electricfield at the opening edge portions 146 of the gate trenches 142 (theouter gate trench 222) can be suppressed.

FIG. 29 is an enlarged view of a region corresponding to FIG. 23 and isan enlarged view of an SiC semiconductor device 231 according to a fifthpreferred embodiment of the present invention. In the following,structures corresponding to the structures described with the SiCsemiconductor device 101 shall be provided with the same reference signsand description thereof shall be omitted.

Referring to FIG. 29, in this embodiment, the SiC epitaxial layer 107includes the high concentration region 108, the low concentration region109, and a concentration gradient region 232, interposed between thehigh concentration region 108 and the low concentration region 109. Inthe SiC epitaxial layer 107, the concentration gradient region 232 isformed in the outer region 112 as well as in the active region 111. Theconcentration gradient region 232 is formed in an entire area of the SiCepitaxial layer 107.

The concentration gradient region 232 has a concentration gradient inwhich the n type impurity concentration decreases gradually from thehigh concentration region 108 toward the low concentration region 109.In other words, the concentration gradient region 232 has aconcentration gradient in which the n type impurity concentrationincreases gradually from the low concentration region 109 toward thehigh concentration region 108. The concentration gradient region 232suppresses sudden change of the n type impurity concentration in aregion between the high concentration region 108 and the lowconcentration region 109.

When the SiC epitaxial layer 107 includes the concentration gradientregion 232, the n type impurity concentration of the high concentrationregion 108 is preferably not less than 1.5 times and not more than 5times the n type impurity concentration of the low concentration region109. The n type impurity concentration of the high concentration region108 may be not less than 3 times and not more than 5 times the n typeimpurity concentration of the low concentration region 109.

A thickness of the concentration gradient region 232 may be not lessthan 0.5 μm and not more than 2.0 μm. The thickness of the concentrationgradient region 232 may be not less than 0.5 μm and not more than 1.0μm, not less than 1.0 μm and not more than 1.5 μm, or not less than 1.5μm and not more than 2.0 μm.

Although a specific description shall be omitted, the gate trenches 142,the source trenches 155, the deep well regions 165, the outer deep wellregion 182, etc., described above are formed in the high concentrationregion 108. That is, the gate trenches 142, the source trenches 155, thedeep well regions 165, the outer deep well region 182, etc., describedabove are formed in a region of the SiC semiconductor layer 102 at thefirst main surface 103 side of a boundary region between the highconcentration region 108 and the concentration gradient region 232.

As described above, even with the semiconductor device 231, the sameeffects as the effects described for the SiC semiconductor device 101can be exhibited.

FIG. 30 is an enlarged view of a region corresponding to FIG. 20 and isan enlarged view of an SiC semiconductor device 241 according to a sixthpreferred embodiment of the present invention. In the following,structures corresponding to the structures described with the SiCsemiconductor device 101 shall be provided with the same reference signsand description thereof shall be omitted.

Referring to FIG. 30, in this embodiment, a gate trench 142 is formed ina lattice shape in plan view. More specifically, the gate trench 142includes a plurality of first gate trenches 242 and a plurality ofsecond gate trenches 243. The plurality of first gate trenches 242 andthe plurality of second gate trenches 243 form active trench portions143.

The plurality of first gate trenches 242 are formed at intervals in thesecond direction Y and are each formed in a band shape extending alongthe first direction X. The plurality of first gate trenches 242 areformed in a stripe shape as a whole in plan view. Side walls of eachfirst gate trench 242 that form long sides are formed by the a-planes ofthe SiC monocrystal. The side walls of each first gate trench 242 thatform short sides are formed by the m-planes of the SiC monocrystal.

The plurality of second gate trenches 243 are formed at intervals in thefirst direction X and are each formed in a band shape extending alongthe second direction Y. The plurality of second gate trenches 243 areformed in a stripe shape as a whole in plan view. Side walls of eachsecond gate trench 243 that form long sides are formed by the m-planesof the SiC monocrystal. The side walls of each second gate trench 243that form short sides are formed by the a-planes of the SiC monocrystal.

The plurality of first gate trenches 242 and the plurality of secondgate trenches 243 intersect each other. A single gate trench 142 oflattice shape in plan view is thereby formed. A plurality of cellregions 244 are demarcated in regions surrounded by the gate trench 142.

The plurality of cell regions 244 are arranged in a matrix at intervalsin the first direction X and the second direction Y in plan view. Theplurality of cell regions 244 are formed in quadrilateral shapes in planview. In each cell region 244, the body region 141 is exposed from theside walls of the gate trench 142. The body region 141 is exposed fromthe side walls of the gate trench 142 that are formed by the m-planesand the a-planes of the SiC monocrystal.

Obviously, the gate trench 142 may be formed in a honeycomb shape inplan view as one mode of the lattice shape. In this case, the pluralityof cell regions 244 may be arranged in a staggered arrangement atintervals in the first direction X and the second direction Y. Also, inthis case, the plurality of cell regions 244 may be formed in hexagonalshapes in plan view.

Each source trench 155 is formed in a central portion of thecorresponding cell region 244 in plan view. Each source trench 155 isformed in a pattern appearing singly at a cut surface appearing when thecorresponding cell region 244 is cut along the first direction X. Also,each source trench 155 is formed in a pattern appearing singly at a cutsurface appearing when the corresponding cell region 244 is cut alongthe second direction Y.

More specifically, each source trench 155 is formed in a quadrilateralshape in plan view. Four side walls of each source trench 155 are formedby the m-planes and the a-planes of the SiC monocrystal. A planar shapeof each source trench 155 is arbitrary. Each source trench 155 may beformed in a polygonal shape, such as a triangular shape, pentagonalshape, hexagonal shape, etc., or a circular shape or elliptical shape inplan view.

A sectional view taken along line XXI-XXI of FIG. 30 corresponds to thesectional view of FIG. 21. A sectional view taken along line XXII-XXIIof FIG. 30 corresponds to the sectional view of FIG. 22.

As described above, even with the SiC semiconductor device 241, the sameeffects as the effects described for the SiC semiconductor device 101can be exhibited.

FIG. 31 is a perspective view showing an SiC semiconductor device 251according to a seventh preferred embodiment of the present invention andis a perspective view showing a structure applied with the modifiedlines 22A to 22D according to the first configuration example. In thefollowing, structures corresponding to the structures described with theSiC semiconductor device 101 shall be provided with the same referencesigns and description thereof shall be omitted.

In this embodiment, the modified lines 22A to 22D according to the firstconfiguration example are applied. However, the modified lines 22A to22D according to the second configuration example, third configurationexample, fourth configuration example, fifth configuration example,sixth configuration example, or seventh configuration example may beadopted in place of or in addition to the modified lines 22A to 22Daccording to the first configuration example. Also, the modified lines22A to 22D having configurations combining at least two features amongthe features of the modified lines 22A to 22D according to the first toseventh configuration examples may be adopted.

Referring to FIG. 31, in this embodiment, the side surfaces 126A to 126Dof the passivation layer 125 are continuous to the insulating sidesurfaces 114A to 114D of the main surface insulating layer 113. That is,the side surfaces 105A to 105D, the insulating side surfaces 114A to114D of the main surface insulating layer 113, and the side surfaces126A to 126D of the passivation layer 125 are formed flush with eachother.

In this embodiment, the boundary modified lines 30A to 30D include thirdregions 92 formed at the side surfaces 126A to 126D of the passivationlayer 125. With the exception of the point of being formed at the sidesurfaces 126A to 126D of the passivation layer 125, the structure of theboundary modified lines 30A to 30D of the SiC semiconductor device 251is the same as the structure of the boundary modified lines 30A to 30Dof the SiC semiconductor device 91 (second preferred embodiment).

The description of the boundary modified lines 30A to 30D of the SiCsemiconductor device 91 applies to the description of the boundarymodified lines 30A to 30D of the SiC semiconductor device 251. Specificdescription of the boundary modified lines 30A to 30D of the SiCsemiconductor device 251 shall be omitted.

As described above, even with the SiC semiconductor device 251, the sameeffects as the effects described for the SiC semiconductor device 101can be exhibited.

Preferred embodiments of the present invention may be implemented in yetother embodiments.

With each of the preferred embodiments described above, an embodimentwhere the side surface 5A or 105A and the side surface 5C or 105C of theSiC semiconductor layer 2 or 102 face the a-planes of the SiCmonocrystal and the side surface 5B or 105B and the side surface 5D or105D face the m-planes of the SiC monocrystal was described. However, anembodiment where the side surface 5A or 105A and the side surface 5C or105C face the m-planes of the SiC monocrystal and the side surface 5B or105B and the side surface 5D or 105D face the a-planes of the SiCmonocrystal may be adopted.

With each of the preferred embodiments described above, an example wherethe modified lines 22A to 22D of band shapes that extend continuouslyare formed was described. However, in each of the preferred embodimentsdescribed above, the modified lines 22A to 22D of broken-line bandshapes (broken line shapes) may be formed. That is, the modified lines22A to 22D may be formed in band shapes extending intermittently. Inthis case, one, two or three of the modified lines 22A to 22D may beformed in a broken-line band shape and the remainder may be formed in aband shape.

With each of the third to seventh preferred embodiments described above,an example where the plurality of gate trenches 142 (first gate trenches242) extending along the m-axis direction (the [1-100] direction) of theSiC monocrystal are formed was described. However, the plurality of gatetrenches 142 (first gate trenches 242) extending along the a-axisdirection (the [11-20] direction) of the SiC monocrystal may be formed.In this case, the plurality of source trenches 155 extending along thea-axis direction (the [11-20] direction) of the SiC monocrystal areformed.

With each of the third to seventh preferred embodiments described above,an example where the source electrode layers 157 are embedded in thesource trenches 155 across the source insulating layers 156 wasdescribed. However, the source electrode layers 157 may be embeddeddirectly in the source trenches 155 without interposition of the sourceinsulating layers 156.

With each of the third to seventh preferred embodiments described above,an example where each source insulating layer 156 is formed along theside walls and the bottom wall of the corresponding source trench 155was described. However, each source insulating layer 156 may be formedalong the side walls of the corresponding source trench 155 such as toexpose the bottom wall of the source trench 155. Each source insulatinglayer 156 may be formed along the side walls and the bottom wall of thecorresponding source trench 155 such as to expose a portion of thebottom wall of the source trench 155.

Also, each source insulating layer 156 may be formed along the bottomwall of the corresponding source trench 155 such as to expose the sidewalls of the source trench 155. Each source insulating layer 156 may beformed along the side walls and the bottom wall of the correspondingsource trench 155 such as to expose a portion of the side walls of thesource trench 155.

With each of the third to seventh preferred embodiments described above,an example where the gate electrode layers 149 and the gate wiring layer150 that include the p type polysilicon doped with the p type impurityare formed was described. However, if increase of the gate thresholdvoltage Vth is not emphasized, the gate electrode layers 149 and thegate wiring layer 150 may include the n type polysilicon doped with then type impurity in place of or in addition to the p type polysilicon.

In this case, the low resistance electrode layer 167 may be formed bysiliciding, by a metal material, the portions of the gate electrodelayers 149 (n type polysilicon) forming the surface layer portions. Thatis, the low resistance electrode layer 167 may include an n typepolycide. With such a structure, reduction of gate resistance can beachieved.

In each of the third to seventh preferred embodiments described above, ap⁺ type SiC semiconductor substrate (106) may be adopted in place of then⁺ type SiC semiconductor substrate 106. With this structure, an IGBT(insulated gate bipolar transistor) can be provided in place of aMISFET. In this case, in each of the third to seventh preferredembodiments described above, the “source” of the MISFET is replaced byan “emitter” of the IGBT and the “drain” of the MISFET is replaced by a“collector” of the IGBT.

In each of the preferred embodiments described above, a structure inwhich the conductivity types of the respective semiconductor portionsare inverted may be adopted. That is, a p type portion may be made to beof an n type and an n type portion may be made to be of a p type.

The respective preferred embodiments described above can also be appliedto a semiconductor device using a semiconductor material differing fromSiC. The semiconductor material differing from SiC may be a compoundsemiconductor material. The compound semiconductor material may beeither or both of gallium nitride (GaN) and gallium oxide (Ga₂O₃).

For example, each of the third to seventh preferred embodimentsdescribed above may be a compound semiconductor device that includes avertical type compound semiconductor MISFET adopting a compoundsemiconductor material in place of SiC. In the compound semiconductor,magnesium may be adopted as type impurity (acceptor). Also, germanium(Ge), oxygen (O), or silicon (Si) may be adopted as an n type impurity(donor).

Examples of features extracted from the present description and drawingsare indicated below.

[A1] An SiC semiconductor device including an SiC semiconductor layerincluding an SiC monocrystal and having a first main surface at oneside, a second main surface at another side, and a side surfaceconnecting the first main surface and the second main surface, aninsulating layer including an insulating material, covering the firstmain surface of the SiC semiconductor layer, and having an insulatingside surface continuous to the side surface of the SiC semiconductorlayer, and a fixing layer fixing the side surface of the SiCsemiconductor layer and the insulating side surface of the insulatinglayer.

According to this SiC semiconductor device, the SiC semiconductor devicein which peeling of the insulating layer can be suppressed by the fixinglayer can be provided.

[A2] The SiC semiconductor device according to A1, wherein the fixinglayer includes a weld layer welding the side surface of the SiCsemiconductor layer and the insulating side surface of the insulatinglayer.

[A3] The SiC semiconductor device according to A1 or A2, wherein thefixing layer extends in a band shape along a tangential direction to thefirst main surface of the SiC semiconductor layer.

[A4] The SiC semiconductor device according to any one of A1 to A3,wherein the fixing layer includes boundary modifying layer including afirst region that is modified to be of a property differing from the SiCmonocrystal and a second region that is modified to be of a propertydiffering from the insulating material of the insulating layer, andbeing formed across the side surface of the SiC semiconductor layer andthe insulating side surface of the insulating layer.

[A5] The SiC semiconductor device according to any one of A1 to A4,wherein the SiC semiconductor layer has a laminated structure thatincludes an SiC semiconductor substrate and an SiC epitaxial layer andin which the first main surface is formed by the SiC epitaxial layer,the insulating layer is formed on the SiC epitaxial layer, and thefixing layer is formed across the SiC epitaxial layer and the insulatinglayer.

The present description does not restrict any combined embodiment offeatures illustrated with the first to seventh preferred embodiments.The first to seventh preferred embodiments may be combined among eachother in any mode or any embodiment. That is, an SiC semiconductordevice combining features illustrated with the first to seventhpreferred embodiments in any mode or any configuration may be adopted.

The present application corresponds to Japanese Patent Application No.2018-151449 filed on Aug. 10, 2018 in the Japan Patent Office, and theentire disclosure of this applications is incorporated herein byreference.

While preferred embodiments of the present invention have been describedin detail, these are merely specific examples used to clarify thetechnical contents of the present invention and the present inventionshould not be interpreted as being limited to these specific examplesand the scope of the present invention is to be limited only by theappended claims.

REFERENCE SIGNS LIST

-   1 SiC semiconductor device-   2 SiC semiconductor layer-   3 first main surface of SiC semiconductor layer-   4 second main surface of SiC semiconductor layer-   5A side surface of SiC semiconductor layer-   5B side surface of SiC semiconductor layer-   5C side surface of SiC semiconductor layer-   5D side surface of SiC semiconductor layer-   6 SiC semiconductor substrate-   7 SiC epitaxial layer-   10 main surface insulating layer-   11A insulating side surface of main surface insulating layer-   11B insulating side surface of main surface insulating layer-   11C insulating side surface of main surface insulating layer-   11D insulating side surface of main surface insulating layer-   13 passivation layer-   16 resin layer-   22A modified line-   22B modified line-   22C modified line-   22D modified line-   30A boundary modified line-   30B boundary modified line-   30C boundary modified line-   30D boundary modified line-   31 first region of boundary modified line-   32 second region of boundary modified line-   33 a-plane boundary modified portion (boundary modified portion)-   34 m-plane boundary modified portion (boundary modified portion)-   91 SiC semiconductor device-   101 SiC semiconductor device-   102 SiC semiconductor layer-   103 first main surface of SiC semiconductor layer-   104 second main surface of SiC semiconductor layer-   105A side surface of SiC semiconductor layer-   105B side surface of SiC semiconductor layer-   105C side surface of SiC semiconductor layer-   105D side surface of SiC semiconductor layer-   106 SiC semiconductor substrate-   107 SiC epitaxial layer-   113 main surface insulating layer-   114A insulating side surface of main surface insulating layer-   114B insulating side surface of main surface insulating layer-   114C insulating side surface of main surface insulating layer-   114D insulating side surface of main surface insulating layer-   125 passivation layer-   129 resin layer-   θ off angle-   Z normal direction-   X first direction (tangential direction)-   Y second direction (tangential direction)

1. An SiC semiconductor device comprising: an SiC semiconductor layerincluding an SiC monocrystal and having a first main surface as a devicesurface, a second main surface at a side opposite to the first mainsurface, and a side surface connecting the first main surface and thesecond main surface; a main surface insulating layer including aninsulating material, covering the first main surface of the SiCsemiconductor layer, and having an insulating side surface continuous tothe side surface of the SiC semiconductor layer; and a boundary modifiedlayer including a first region that is modified to be of a propertydiffering from the SiC monocrystal and a second region that is modifiedto be of a property differing from the insulating material, and beingformed across the side surface of the SiC semiconductor layer and theinsulating side surface of the main surface insulating layer. 2.(canceled)
 3. The SiC semiconductor device according to claim 1, whereinthe boundary modified layer extends in a band shape along a tangentialdirection to the first main surface of the SiC semiconductor layer. 4.The SiC semiconductor device according to claim 1, wherein the boundarymodified layer includes a plurality of boundary modified portions eachextending in a normal direction to the first main surface of the SiCsemiconductor layer and aligned such as to oppose each other in atangential direction to the first main surface of the SiC semiconductorlayer.
 5. The SiC semiconductor device according to claim 1, wherein themain surface insulating layer includes SiO₂.
 6. The SiC semiconductordevice according to claim 1, wherein the side surface of the SiCsemiconductor layer is constituted of a cleavage surface, and theinsulating side surface of the main surface insulating layer isconstituted of a cleavage surface.
 7. (canceled)
 8. The SiCsemiconductor device according to claim 1, further comprising: aninsulating layer formed on the main surface insulating layer; whereinthe boundary modified layer is formed across the side surface of the SiCsemiconductor layer and the insulating side surface of the main surfaceinsulating layer while avoiding the insulating layer.
 9. The SiCsemiconductor device according to claim 8, wherein the insulating layeris formed at an interval toward an inner side from the side surface ofthe SiC semiconductor layer.
 10. The SiC semiconductor device accordingto claim 9, wherein the insulating layer is formed at an interval of notless than 1 μm toward the inner side from the side surface of the SiCsemiconductor layer.
 11. The SiC semiconductor device according to claim8, wherein the insulating layer has a thickness of not less than 1 μm.12. The SiC semiconductor device according to claim 8, wherein theinsulating layer includes an insulating material differing from the mainsurface insulating layer.
 13. The SiC semiconductor device according toclaim 8, wherein the insulating layer includes a resin layer formed onthe main surface insulating layer.
 14. The SiC semiconductor deviceaccording to claim 8, wherein the insulating layer includes apassivation layer formed on the main surface insulating layer. 15.(canceled)
 16. The SiC semiconductor device according to claim 1,further comprising: a modified layer formed in a region of the sidesurface of the SiC semiconductor layer at the second main surface sideof the SiC semiconductor layer with respect to the boundary modifiedlayer, and being modified to be of a property differing from the SiCmonocrystal.
 17. The SiC semiconductor device according to claim 16,wherein the modified layer extends in a band shape along a tangentialdirection to the first main surface of the SiC semiconductor layer. 18.The SiC semiconductor device according to claim 1, wherein the SiCsemiconductor layer has a thickness of not less than 40 μm and not morethan 200 μm.
 19. The SiC semiconductor device according to claim 1,wherein the SiC semiconductor layer has a laminated structure thatincludes an SiC semiconductor substrate and an SiC epitaxial layer andin which the first main surface is formed by the SiC epitaxial layer,the main surface insulating layer is formed on the SiC epitaxial layer,and the boundary modified layer is formed across the SiC epitaxial layerand the main surface insulating layer.
 20. The SiC semiconductor deviceaccording to claim 19, wherein the SiC epitaxial layer has a thicknessnot more than a thickness of the SiC semiconductor substrate.
 21. TheSiC semiconductor device according to claim 19, wherein the SiCsemiconductor substrate has a thickness of not less than 40 μm and notmore than 150 μm, and the SiC epitaxial layer has a thickness of notless than 1 μm and not more than 50 μm.
 22. The SiC semiconductor deviceaccording to claim 1, wherein the SiC monocrystal is constituted of ahexagonal crystal, and the first main surface of the SiC semiconductorlayer faces a c-plane of the SiC monocrystal. 23-24. (canceled)
 25. TheSiC semiconductor device according to claim 22, wherein the first mainsurface of the SiC semiconductor layer has an off angle inclined at anangle of not less than 0° and not more than 10° with respect to thec-plane of the SiC monocrystal. 26-27. (canceled)